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Revert "Merge branch 'pr/446' into 420"

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This reverts commit 761dc48b3e, reversing
changes made to 91f037c63f.
This commit is contained in:
RogueMaster
2022-11-25 03:08:53 -05:00
parent d9e7780fb9
commit 28cc99ad2d
40 changed files with 184 additions and 3617 deletions
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lib/nfc/protocols/nfca.c
+41 -76
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@@ -2,27 +2,19 @@
#include <string.h>
#include <stdio.h>
#include <furi.h>
#include <furi_hal_gpio.h>
#include <furi_hal_resources.h>
#define NFCA_CMD_RATS (0xE0U)
#define NFCA_CRC_INIT (0x6363)
#define NFCA_F_SIG (13560000.0) /* [Hz] NFC frequency */
#define NFCA_F_SUB (NFCA_F_SIG/16) /* [Hz] NFC subcarrier frequency fs/16 (847500 Hz) */
#define T_SUB (1000000000000.0f / NFCA_F_SUB) /* [ps] subcarrier period = 1/NFCA_F_SUB (1.18 µs) */
#define T_SUB_PHASE (T_SUB/2) /* [ps] a single subcarrier phase (590 µs) */
#define NFCA_F_SIG (13560000.0)
#define T_SIG 7374 //73.746ns*100
#define T_SIG_x8 58992 //T_SIG*8
#define T_SIG_x8_x8 471936 //T_SIG*8*8
#define T_SIG_x8_x9 530928 //T_SIG*8*9
#define NFCA_SIGNAL_MAX_EDGES (1350)
#define SEQ_SOF 0
#define SEQ_BIT0 1
#define SEQ_BIT1 2
#define SEQ_EOF 3
#define SEQ_IDLE 4
typedef struct {
uint8_t cmd;
uint8_t param;
@@ -71,69 +63,46 @@ bool nfca_emulation_handler(
return sleep;
}
static void nfca_add_bit(DigitalSignal* signal, bool bit) {
if(bit) {
signal->start_level = true;
for(size_t i = 0; i < 7; i++) {
signal->edge_timings[i] = T_SIG_x8;
}
signal->edge_timings[7] = T_SIG_x8_x9;
signal->edge_cnt = 8;
} else {
signal->start_level = false;
signal->edge_timings[0] = T_SIG_x8_x8;
for(size_t i = 1; i < 9; i++) {
signal->edge_timings[i] = T_SIG_x8;
}
signal->edge_cnt = 9;
}
}
static void nfca_add_byte(NfcaSignal* nfca_signal, uint8_t byte, bool parity) {
for(uint8_t i = 0; i < 8; i++) {
if(byte & (1 << i)) {
digital_sequence_add(nfca_signal->tx_signal, SEQ_BIT1);
digital_signal_append(nfca_signal->tx_signal, nfca_signal->one);
} else {
digital_sequence_add(nfca_signal->tx_signal, SEQ_BIT0);
digital_signal_append(nfca_signal->tx_signal, nfca_signal->zero);
}
}
if(parity) {
digital_sequence_add(nfca_signal->tx_signal, SEQ_BIT1);
digital_signal_append(nfca_signal->tx_signal, nfca_signal->one);
} else {
digital_sequence_add(nfca_signal->tx_signal, SEQ_BIT0);
}
}
static void nfca_add_modulation(DigitalSignal* signal, size_t phases) {
for(size_t i = 0; i < phases; i++) {
signal->edge_timings[signal->edge_cnt++] = DIGITAL_SIGNAL_PS(T_SUB_PHASE);
}
}
static void nfca_add_silence(DigitalSignal* signal, size_t phases) {
bool end_level = signal->start_level ^ ((signal->edge_cnt % 2) == 0);
if((signal->edge_cnt == 0) || end_level) {
signal->edge_timings[signal->edge_cnt++] = DIGITAL_SIGNAL_PS(phases * T_SUB_PHASE);
} else {
signal->edge_timings[signal->edge_cnt - 1] += DIGITAL_SIGNAL_PS(phases * T_SUB_PHASE);
digital_signal_append(nfca_signal->tx_signal, nfca_signal->zero);
}
}
NfcaSignal* nfca_signal_alloc() {
NfcaSignal* nfca_signal = malloc(sizeof(NfcaSignal));
/* ISO14443-2 defines 3 sequences for type A communication */
nfca_signal->seq_d = digital_signal_alloc(10);
nfca_signal->seq_e = digital_signal_alloc(10);
nfca_signal->seq_f = digital_signal_alloc(10);
/* SEQ D has the first half modulated, used as SOF */
nfca_signal->seq_d->start_level = true;
nfca_add_modulation(nfca_signal->seq_d, 8);
nfca_add_silence(nfca_signal->seq_d, 8);
/* SEQ E has the second half modulated */
nfca_signal->seq_e->start_level = false;
nfca_add_silence(nfca_signal->seq_e, 8);
nfca_add_modulation(nfca_signal->seq_e, 8);
/* SEQ F is just no modulation, used as EOF */
nfca_signal->seq_f->start_level = false;
nfca_add_silence(nfca_signal->seq_f, 16);
nfca_signal->tx_signal = digital_sequence_alloc(NFCA_SIGNAL_MAX_EDGES, &gpio_spi_r_mosi);
/* we are dealing with shorter sequences, enable bake-before-sending */
//nfca_signal->tx_signal->bake = true;
digital_sequence_set_signal(nfca_signal->tx_signal, SEQ_SOF, nfca_signal->seq_d);
digital_sequence_set_signal(nfca_signal->tx_signal, SEQ_BIT0, nfca_signal->seq_e);
digital_sequence_set_signal(nfca_signal->tx_signal, SEQ_BIT1, nfca_signal->seq_d);
digital_sequence_set_signal(nfca_signal->tx_signal, SEQ_EOF, nfca_signal->seq_f);
digital_sequence_set_signal(nfca_signal->tx_signal, SEQ_IDLE, nfca_signal->seq_f);
nfca_signal->one = digital_signal_alloc(10);
nfca_signal->zero = digital_signal_alloc(10);
nfca_add_bit(nfca_signal->one, true);
nfca_add_bit(nfca_signal->zero, false);
nfca_signal->tx_signal = digital_signal_alloc(NFCA_SIGNAL_MAX_EDGES);
return nfca_signal;
}
@@ -141,10 +110,9 @@ NfcaSignal* nfca_signal_alloc() {
void nfca_signal_free(NfcaSignal* nfca_signal) {
furi_assert(nfca_signal);
digital_signal_free(nfca_signal->seq_d);
digital_signal_free(nfca_signal->seq_e);
digital_signal_free(nfca_signal->seq_f);
digital_sequence_free(nfca_signal->tx_signal);
digital_signal_free(nfca_signal->one);
digital_signal_free(nfca_signal->zero);
digital_signal_free(nfca_signal->tx_signal);
free(nfca_signal);
}
@@ -153,18 +121,17 @@ void nfca_signal_encode(NfcaSignal* nfca_signal, uint8_t* data, uint16_t bits, u
furi_assert(data);
furi_assert(parity);
digital_sequence_clear(nfca_signal->tx_signal);
/* add some idle bit times before SOF in case the GPIO was active */
digital_sequence_add(nfca_signal->tx_signal, SEQ_IDLE);
digital_sequence_add(nfca_signal->tx_signal, SEQ_SOF);
nfca_signal->tx_signal->edge_cnt = 0;
nfca_signal->tx_signal->start_level = true;
// Start of frame
digital_signal_append(nfca_signal->tx_signal, nfca_signal->one);
if(bits < 8) {
for(size_t i = 0; i < bits; i++) {
if(FURI_BIT(data[0], i)) {
digital_sequence_add(nfca_signal->tx_signal, SEQ_BIT1);
digital_signal_append(nfca_signal->tx_signal, nfca_signal->one);
} else {
digital_sequence_add(nfca_signal->tx_signal, SEQ_BIT0);
digital_signal_append(nfca_signal->tx_signal, nfca_signal->zero);
}
}
} else {
@@ -172,6 +139,4 @@ void nfca_signal_encode(NfcaSignal* nfca_signal, uint8_t* data, uint16_t bits, u
nfca_add_byte(nfca_signal, data[i], parity[i / 8] & (1 << (7 - (i & 0x07))));
}
}
digital_sequence_add(nfca_signal->tx_signal, SEQ_EOF);
}