mirror of
https://github.com/Next-Flip/Momentum-Firmware.git
synced 2026-05-13 03:28:36 -07:00
updated protoview and fixed array count issue
arrays start at 0 and citroen_tpms was trying to read 0-10 meaning 11 full bytes rather than actually 10 (0-9).
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@@ -11,7 +11,7 @@
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*
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* ((256+MDMCFG3)*(2^MDMCFG4:0..3bits)) / 2^28 * 26000000.
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*
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* For instance for the default values of MDMCFG3 (34) and MDMCFG4 (12):
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* For instance for the default values of MDMCFG3[0..3] (34) and MDMCFG4 (12):
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*
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* ((256+34)*(2^12))/(2^28)*26000000 = 115051.2688000000, that is 115KBaud
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*
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@@ -38,6 +38,23 @@
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* d 82 khz
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* e 68 khz
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* f 58 khz
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*
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* FSK deviation is controlled by the DEVIATION register. In Ruby:
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*
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* dev = (26000000.0/2**17)*(8+(deviation&7))*(2**(deviation>>4&7))
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*
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* deviation&7 (last three bits) is the deviation mantissa, while
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* deviation>>4&7 (bits 6,5,4) are the exponent.
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*
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* Deviations values according to certain configuration of DEVIATION:
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*
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* 0x04 -> 2.380371 kHz
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* 0x24 -> 9.521484 kHz
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* 0x34 -> 19.042969 Khz
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* 0x40 -> 25.390625 Khz
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* 0x43 -> 34.912109 Khz
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* 0x45 -> 41.259765 Khz
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* 0x47 -> 47.607422 kHz
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*/
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/* 20 KBaud, 2FSK, 28.56 kHz deviation, 325 Khz bandwidth filter. */
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@@ -130,3 +147,46 @@ static uint8_t protoview_subghz_tpms2_async_regs[][2] = {
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{0, 0},
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};
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/* Parameters that should work well for the TPMS PVM C210 sensor. */
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static uint8_t protoview_subghz_tpms3_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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{CC1101_PKTCTRL1, 0x04},
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// // Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x02}, // 2 is the channel spacing exponet: not used
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{CC1101_MDMCFG2, 0x10}, // GFSK without any other check
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{CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud
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{CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz
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{CC1101_DEVIATN, 0x34}, // Deviation 19.04 Khz, works well with TPMS
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0, 0x80},
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{CC1101_AGCCTRL1, 0x58},
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{CC1101_AGCCTRL2, 0x87},
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
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{CC1101_FREND1, 0x56},
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/* End */
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{0, 0},
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};
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