[FL-3375] SubGhz: add CC1101 module external (#2747)

* SubGhz: add CC1101 Ext driver
* SubGhz:  move TIM2 -> TIM17 use cc1101_ext
* FuriHal: SPI move channel DMA 3,4 -> 6.7
* Documentation: fix font
* SubGhz: add work with SubGhz devices by link to device
* SubGhz: add support switching external/internal cc1101 "subghz chat"
* SubGhz: add support switching external/internal cc1101 "subghz tx" and "subghz rx"
* SubGhz: add "Radio Settings" scene
* SubGhz: add icon
* SubGhz: add supported CC1101 external module in SubGhz app
* SubGhz: fix check frequency supported radio device
* SubGhz: fix clang-formatted
* Sughz: move dirver CC1101_Ext to lib , compile cmd ./fbt launch_app APPSRC=radio_device_cc1101_ext
* SubGhz: fix CLI
* SubGhz: fix PVS
* SubGhz: delete comments
* SubGhz: fix unit_test
* Format sources
* Update api symbols and drivers targets
* Drivers: find proper place for target option
* SubGhz: external device connected method naming
* Format sources
* SubGhz:  fix module selection menu, when external is not connected
* SubGhz: fix furi_assert(device);
* SubGhz: fix split h and c
* SubGhz: furi_hal_subghz remove preset load function by name
* SubGhz: deleted comments
* Format Sources
* SubGhz: add some consts and fix unit tests
* Sync API Symbols

Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>

firmware/targets/f7/api_symbols.csv

@@ -1,5 +1,5 @@
 entry,status,name,type,params
-Version,+,31.3,,
+Version,+,32.0,,
 Header,+,applications/services/bt/bt_service/bt.h,,
 Header,+,applications/services/cli/cli.h,,
 Header,+,applications/services/cli/cli_vcp.h,,
@@ -56,7 +56,6 @@ Header,+,firmware/targets/f7/furi_hal/furi_hal_rfid.h,,
 Header,+,firmware/targets/f7/furi_hal/furi_hal_spi_config.h,,
 Header,+,firmware/targets/f7/furi_hal/furi_hal_spi_types.h,,
 Header,+,firmware/targets/f7/furi_hal/furi_hal_subghz.h,,
-Header,+,firmware/targets/f7/furi_hal/furi_hal_subghz_configs.h,,
 Header,+,firmware/targets/f7/furi_hal/furi_hal_target_hw.h,,
 Header,+,firmware/targets/f7/furi_hal/furi_hal_uart.h,,
 Header,+,firmware/targets/f7/furi_hal/furi_hal_usb_cdc.h,,
@@ -186,6 +185,7 @@ Header,+,lib/subghz/blocks/decoder.h,,
 Header,+,lib/subghz/blocks/encoder.h,,
 Header,+,lib/subghz/blocks/generic.h,,
 Header,+,lib/subghz/blocks/math.h,,
+Header,+,lib/subghz/devices/cc1101_configs.h,,
 Header,+,lib/subghz/environment.h,,
 Header,+,lib/subghz/protocols/raw.h,,
 Header,+,lib/subghz/receiver.h,,
@@ -317,6 +317,7 @@ Function,-,LL_mDelay,void,uint32_t
 Function,-,SystemCoreClockUpdate,void,
 Function,-,SystemInit,void,
 Function,-,_Exit,void,int
+Function,+,__aeabi_uldivmod,void*,"uint64_t, uint64_t"
 Function,-,__assert,void,"const char*, int, const char*"
 Function,+,__assert_func,void,"const char*, int, const char*, const char*"
 Function,+,__clear_cache,void,"void*, void*"
@@ -657,26 +658,6 @@ Function,+,canvas_width,uint8_t,const Canvas*
 Function,-,cbrt,double,double
 Function,-,cbrtf,float,float
 Function,-,cbrtl,long double,long double
-Function,+,cc1101_calibrate,void,FuriHalSpiBusHandle*
-Function,+,cc1101_flush_rx,void,FuriHalSpiBusHandle*
-Function,+,cc1101_flush_tx,void,FuriHalSpiBusHandle*
-Function,-,cc1101_get_partnumber,uint8_t,FuriHalSpiBusHandle*
-Function,+,cc1101_get_rssi,uint8_t,FuriHalSpiBusHandle*
-Function,+,cc1101_get_status,CC1101Status,FuriHalSpiBusHandle*
-Function,-,cc1101_get_version,uint8_t,FuriHalSpiBusHandle*
-Function,+,cc1101_read_fifo,uint8_t,"FuriHalSpiBusHandle*, uint8_t*, uint8_t*"
-Function,+,cc1101_read_reg,CC1101Status,"FuriHalSpiBusHandle*, uint8_t, uint8_t*"
-Function,+,cc1101_reset,void,FuriHalSpiBusHandle*
-Function,+,cc1101_set_frequency,uint32_t,"FuriHalSpiBusHandle*, uint32_t"
-Function,-,cc1101_set_intermediate_frequency,uint32_t,"FuriHalSpiBusHandle*, uint32_t"
-Function,+,cc1101_set_pa_table,void,"FuriHalSpiBusHandle*, const uint8_t[8]"
-Function,+,cc1101_shutdown,void,FuriHalSpiBusHandle*
-Function,+,cc1101_strobe,CC1101Status,"FuriHalSpiBusHandle*, uint8_t"
-Function,+,cc1101_switch_to_idle,void,FuriHalSpiBusHandle*
-Function,+,cc1101_switch_to_rx,void,FuriHalSpiBusHandle*
-Function,+,cc1101_switch_to_tx,void,FuriHalSpiBusHandle*
-Function,+,cc1101_write_fifo,uint8_t,"FuriHalSpiBusHandle*, const uint8_t*, uint8_t"
-Function,+,cc1101_write_reg,CC1101Status,"FuriHalSpiBusHandle*, uint8_t, uint8_t"
 Function,-,ceil,double,double
 Function,-,ceilf,float,float
 Function,-,ceill,long double,long double
@@ -1383,6 +1364,7 @@ Function,+,furi_hal_spi_release,void,FuriHalSpiBusHandle*
 Function,-,furi_hal_subghz_dump_state,void,
 Function,+,furi_hal_subghz_flush_rx,void,
 Function,+,furi_hal_subghz_flush_tx,void,
+Function,+,furi_hal_subghz_get_data_gpio,const GpioPin*,
 Function,+,furi_hal_subghz_get_lqi,uint8_t,
 Function,+,furi_hal_subghz_get_rssi,float,
 Function,+,furi_hal_subghz_idle,void,
@@ -1390,10 +1372,9 @@ Function,-,furi_hal_subghz_init,void,
 Function,+,furi_hal_subghz_is_async_tx_complete,_Bool,
 Function,+,furi_hal_subghz_is_frequency_valid,_Bool,uint32_t
 Function,+,furi_hal_subghz_is_rx_data_crc_valid,_Bool,
-Function,+,furi_hal_subghz_load_custom_preset,void,uint8_t*
+Function,+,furi_hal_subghz_load_custom_preset,void,const uint8_t*
 Function,+,furi_hal_subghz_load_patable,void,const uint8_t[8]
-Function,+,furi_hal_subghz_load_preset,void,FuriHalSubGhzPreset
-Function,+,furi_hal_subghz_load_registers,void,uint8_t*
+Function,+,furi_hal_subghz_load_registers,void,const uint8_t*
 Function,+,furi_hal_subghz_read_packet,void,"uint8_t*, uint8_t*"
 Function,+,furi_hal_subghz_reset,void,
 Function,+,furi_hal_subghz_rx,void,
@@ -1401,7 +1382,7 @@ Function,+,furi_hal_subghz_rx_pipe_not_empty,_Bool,
 Function,+,furi_hal_subghz_set_async_mirror_pin,void,const GpioPin*
 Function,+,furi_hal_subghz_set_frequency,uint32_t,uint32_t
 Function,+,furi_hal_subghz_set_frequency_and_path,uint32_t,uint32_t
-Function,+,furi_hal_subghz_set_path,void,FuriHalSubGhzPath
+Function,-,furi_hal_subghz_set_path,void,FuriHalSubGhzPath
 Function,-,furi_hal_subghz_shutdown,void,
 Function,+,furi_hal_subghz_sleep,void,
 Function,+,furi_hal_subghz_start_async_rx,void,"FuriHalSubGhzCaptureCallback, void*"
@@ -2686,6 +2667,36 @@ Function,+,subghz_block_generic_deserialize,SubGhzProtocolStatus,"SubGhzBlockGen
 Function,+,subghz_block_generic_deserialize_check_count_bit,SubGhzProtocolStatus,"SubGhzBlockGeneric*, FlipperFormat*, uint16_t"
 Function,+,subghz_block_generic_get_preset_name,void,"const char*, FuriString*"
 Function,+,subghz_block_generic_serialize,SubGhzProtocolStatus,"SubGhzBlockGeneric*, FlipperFormat*, SubGhzRadioPreset*"
+Function,+,subghz_devices_begin,_Bool,const SubGhzDevice*
+Function,+,subghz_devices_deinit,void,
+Function,+,subghz_devices_end,void,const SubGhzDevice*
+Function,+,subghz_devices_flush_rx,void,const SubGhzDevice*
+Function,+,subghz_devices_flush_tx,void,const SubGhzDevice*
+Function,+,subghz_devices_get_by_name,const SubGhzDevice*,const char*
+Function,+,subghz_devices_get_data_gpio,const GpioPin*,const SubGhzDevice*
+Function,+,subghz_devices_get_lqi,uint8_t,const SubGhzDevice*
+Function,+,subghz_devices_get_name,const char*,const SubGhzDevice*
+Function,+,subghz_devices_get_rssi,float,const SubGhzDevice*
+Function,+,subghz_devices_idle,void,const SubGhzDevice*
+Function,+,subghz_devices_init,void,
+Function,+,subghz_devices_is_async_complete_tx,_Bool,const SubGhzDevice*
+Function,+,subghz_devices_is_connect,_Bool,const SubGhzDevice*
+Function,+,subghz_devices_is_frequency_valid,_Bool,"const SubGhzDevice*, uint32_t"
+Function,+,subghz_devices_is_rx_data_crc_valid,_Bool,const SubGhzDevice*
+Function,+,subghz_devices_load_preset,void,"const SubGhzDevice*, FuriHalSubGhzPreset, uint8_t*"
+Function,+,subghz_devices_read_packet,void,"const SubGhzDevice*, uint8_t*, uint8_t*"
+Function,+,subghz_devices_reset,void,const SubGhzDevice*
+Function,+,subghz_devices_rx_pipe_not_empty,_Bool,const SubGhzDevice*
+Function,+,subghz_devices_set_async_mirror_pin,void,"const SubGhzDevice*, const GpioPin*"
+Function,+,subghz_devices_set_frequency,uint32_t,"const SubGhzDevice*, uint32_t"
+Function,+,subghz_devices_set_rx,void,const SubGhzDevice*
+Function,+,subghz_devices_set_tx,_Bool,const SubGhzDevice*
+Function,+,subghz_devices_sleep,void,const SubGhzDevice*
+Function,+,subghz_devices_start_async_rx,void,"const SubGhzDevice*, void*, void*"
+Function,+,subghz_devices_start_async_tx,_Bool,"const SubGhzDevice*, void*, void*"
+Function,+,subghz_devices_stop_async_rx,void,const SubGhzDevice*
+Function,+,subghz_devices_stop_async_tx,void,const SubGhzDevice*
+Function,+,subghz_devices_write_packet,void,"const SubGhzDevice*, const uint8_t*, uint8_t"
 Function,+,subghz_environment_alloc,SubGhzEnvironment*,
 Function,+,subghz_environment_free,void,SubGhzEnvironment*
 Function,+,subghz_environment_get_alutech_at_4n_rainbow_table_file_name,const char*,SubGhzEnvironment*
@@ -2744,7 +2755,7 @@ Function,+,subghz_protocol_encoder_raw_free,void,void*
 Function,+,subghz_protocol_encoder_raw_stop,void,void*
 Function,+,subghz_protocol_encoder_raw_yield,LevelDuration,void*
 Function,+,subghz_protocol_raw_file_encoder_worker_set_callback_end,void,"SubGhzProtocolEncoderRAW*, SubGhzProtocolEncoderRAWCallbackEnd, void*"
-Function,+,subghz_protocol_raw_gen_fff_data,void,"FlipperFormat*, const char*"
+Function,+,subghz_protocol_raw_gen_fff_data,void,"FlipperFormat*, const char*, const char*"
 Function,+,subghz_protocol_raw_get_sample_write,size_t,SubGhzProtocolDecoderRAW*
 Function,+,subghz_protocol_raw_save_to_file_init,_Bool,"SubGhzProtocolDecoderRAW*, const char*, SubGhzRadioPreset*"
 Function,+,subghz_protocol_raw_save_to_file_pause,void,"SubGhzProtocolDecoderRAW*, _Bool"
@@ -2788,7 +2799,7 @@ Function,+,subghz_tx_rx_worker_free,void,SubGhzTxRxWorker*
 Function,+,subghz_tx_rx_worker_is_running,_Bool,SubGhzTxRxWorker*
 Function,+,subghz_tx_rx_worker_read,size_t,"SubGhzTxRxWorker*, uint8_t*, size_t"
 Function,+,subghz_tx_rx_worker_set_callback_have_read,void,"SubGhzTxRxWorker*, SubGhzTxRxWorkerCallbackHaveRead, void*"
-Function,+,subghz_tx_rx_worker_start,_Bool,"SubGhzTxRxWorker*, uint32_t"
+Function,+,subghz_tx_rx_worker_start,_Bool,"SubGhzTxRxWorker*, const SubGhzDevice*, uint32_t"
 Function,+,subghz_tx_rx_worker_stop,void,SubGhzTxRxWorker*
 Function,+,subghz_tx_rx_worker_write,_Bool,"SubGhzTxRxWorker*, uint8_t*, size_t"
 Function,+,subghz_worker_alloc,SubGhzWorker*,
@@ -3389,6 +3400,12 @@ Variable,+,sequence_set_vibro_on,const NotificationSequence,
 Variable,+,sequence_single_vibro,const NotificationSequence,
 Variable,+,sequence_solid_yellow,const NotificationSequence,
 Variable,+,sequence_success,const NotificationSequence,
+Variable,+,subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs,const uint8_t[],
+Variable,+,subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs,const uint8_t[],
+Variable,+,subghz_device_cc1101_preset_gfsk_9_99kb_async_regs,const uint8_t[],
+Variable,+,subghz_device_cc1101_preset_msk_99_97kb_async_regs,const uint8_t[],
+Variable,+,subghz_device_cc1101_preset_ook_270khz_async_regs,const uint8_t[],
+Variable,+,subghz_device_cc1101_preset_ook_650khz_async_regs,const uint8_t[],
 Variable,+,subghz_protocol_raw,const SubGhzProtocol,
 Variable,+,subghz_protocol_raw_decoder,const SubGhzProtocolDecoder,
 Variable,+,subghz_protocol_raw_encoder,const SubGhzProtocolEncoder,

firmware/targets/f7/furi_hal/furi_hal_spi.c

@@ -12,10 +12,10 @@
 #define TAG "FuriHalSpi"
 
 #define SPI_DMA DMA2
-#define SPI_DMA_RX_CHANNEL LL_DMA_CHANNEL_3
-#define SPI_DMA_TX_CHANNEL LL_DMA_CHANNEL_4
-#define SPI_DMA_RX_IRQ FuriHalInterruptIdDma2Ch3
-#define SPI_DMA_TX_IRQ FuriHalInterruptIdDma2Ch4
+#define SPI_DMA_RX_CHANNEL LL_DMA_CHANNEL_6
+#define SPI_DMA_TX_CHANNEL LL_DMA_CHANNEL_7
+#define SPI_DMA_RX_IRQ FuriHalInterruptIdDma2Ch6
+#define SPI_DMA_TX_IRQ FuriHalInterruptIdDma2Ch7
 #define SPI_DMA_RX_DEF SPI_DMA, SPI_DMA_RX_CHANNEL
 #define SPI_DMA_TX_DEF SPI_DMA, SPI_DMA_TX_CHANNEL
 
@@ -170,18 +170,18 @@ bool furi_hal_spi_bus_trx(
 }
 
 static void spi_dma_isr() {
-#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_3
-    if(LL_DMA_IsActiveFlag_TC3(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_RX_DEF)) {
-        LL_DMA_ClearFlag_TC3(SPI_DMA);
+#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_6
+    if(LL_DMA_IsActiveFlag_TC6(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_RX_DEF)) {
+        LL_DMA_ClearFlag_TC6(SPI_DMA);
         furi_check(furi_semaphore_release(spi_dma_completed) == FuriStatusOk);
     }
 #else
 #error Update this code. Would you kindly?
 #endif
 
-#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_4
-    if(LL_DMA_IsActiveFlag_TC4(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_TX_DEF)) {
-        LL_DMA_ClearFlag_TC4(SPI_DMA);
+#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_7
+    if(LL_DMA_IsActiveFlag_TC7(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_TX_DEF)) {
+        LL_DMA_ClearFlag_TC7(SPI_DMA);
         furi_check(furi_semaphore_release(spi_dma_completed) == FuriStatusOk);
     }
 #else
@@ -241,8 +241,8 @@ bool furi_hal_spi_bus_trx_dma(
         dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
         LL_DMA_Init(SPI_DMA_TX_DEF, &dma_config);
 
-#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_4
-        LL_DMA_ClearFlag_TC4(SPI_DMA);
+#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_7
+        LL_DMA_ClearFlag_TC7(SPI_DMA);
 #else
 #error Update this code. Would you kindly?
 #endif
@@ -315,8 +315,8 @@ bool furi_hal_spi_bus_trx_dma(
         dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
         LL_DMA_Init(SPI_DMA_RX_DEF, &dma_config);
 
-#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_3
-        LL_DMA_ClearFlag_TC3(SPI_DMA);
+#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_6
+        LL_DMA_ClearFlag_TC6(SPI_DMA);
 #else
 #error Update this code. Would you kindly?
 #endif

firmware/targets/f7/furi_hal/furi_hal_subghz.c

@@ -1,6 +1,5 @@
 #include <furi_hal_subghz.h>
-#include <furi_hal_subghz_configs.h>
-
+#include <lib/subghz/devices/cc1101_configs.h>
 #include <furi_hal_region.h>
 #include <furi_hal_version.h>
 #include <furi_hal_rtc.h>
@@ -27,17 +26,36 @@ static uint32_t furi_hal_subghz_debug_gpio_buff[2];
 #define SUBGHZ_DMA_CH1_DEF SUBGHZ_DMA, SUBGHZ_DMA_CH1_CHANNEL
 #define SUBGHZ_DMA_CH2_DEF SUBGHZ_DMA, SUBGHZ_DMA_CH2_CHANNEL
 
+/** SubGhz state */
+typedef enum {
+    SubGhzStateInit, /**< Init pending */
+
+    SubGhzStateIdle, /**< Idle, energy save mode */
+
+    SubGhzStateAsyncRx, /**< Async RX started */
+
+    SubGhzStateAsyncTx, /**< Async TX started, DMA and timer is on */
+    SubGhzStateAsyncTxLast, /**< Async TX continue, DMA completed and timer got last value to go */
+    SubGhzStateAsyncTxEnd, /**< Async TX complete, cleanup needed */
+
+} SubGhzState;
+
+/** SubGhz regulation, receive transmission on the current frequency for the
+ * region */
+typedef enum {
+    SubGhzRegulationOnlyRx, /**only Rx*/
+    SubGhzRegulationTxRx, /**TxRx*/
+} SubGhzRegulation;
+
 typedef struct {
     volatile SubGhzState state;
     volatile SubGhzRegulation regulation;
-    volatile FuriHalSubGhzPreset preset;
     const GpioPin* async_mirror_pin;
 } FuriHalSubGhz;
 
 volatile FuriHalSubGhz furi_hal_subghz = {
     .state = SubGhzStateInit,
     .regulation = SubGhzRegulationTxRx,
-    .preset = FuriHalSubGhzPresetIDLE,
     .async_mirror_pin = NULL,
 };
 
@@ -45,10 +63,13 @@ void furi_hal_subghz_set_async_mirror_pin(const GpioPin* pin) {
     furi_hal_subghz.async_mirror_pin = pin;
 }
 
+const GpioPin* furi_hal_subghz_get_data_gpio() {
+    return &gpio_cc1101_g0;
+}
+
 void furi_hal_subghz_init() {
     furi_assert(furi_hal_subghz.state == SubGhzStateInit);
     furi_hal_subghz.state = SubGhzStateIdle;
-    furi_hal_subghz.preset = FuriHalSubGhzPresetIDLE;
 
     furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
 
@@ -102,8 +123,6 @@ void furi_hal_subghz_sleep() {
     cc1101_shutdown(&furi_hal_spi_bus_handle_subghz);
 
     furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
-
-    furi_hal_subghz.preset = FuriHalSubGhzPresetIDLE;
 }
 
 void furi_hal_subghz_dump_state() {
@@ -115,34 +134,7 @@ void furi_hal_subghz_dump_state() {
     furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
 }
 
-void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
-    if(preset == FuriHalSubGhzPresetOok650Async) {
-        furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_ook_650khz_async_regs);
-        furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
-    } else if(preset == FuriHalSubGhzPresetOok270Async) {
-        furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_ook_270khz_async_regs);
-        furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
-    } else if(preset == FuriHalSubGhzPreset2FSKDev238Async) {
-        furi_hal_subghz_load_registers(
-            (uint8_t*)furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs);
-        furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
-    } else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
-        furi_hal_subghz_load_registers(
-            (uint8_t*)furi_hal_subghz_preset_2fsk_dev47_6khz_async_regs);
-        furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
-    } else if(preset == FuriHalSubGhzPresetMSK99_97KbAsync) {
-        furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_msk_99_97kb_async_regs);
-        furi_hal_subghz_load_patable(furi_hal_subghz_preset_msk_async_patable);
-    } else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
-        furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_gfsk_9_99kb_async_regs);
-        furi_hal_subghz_load_patable(furi_hal_subghz_preset_gfsk_async_patable);
-    } else {
-        furi_crash("SubGhz: Missing config.");
-    }
-    furi_hal_subghz.preset = preset;
-}
-
-void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
+void furi_hal_subghz_load_custom_preset(const uint8_t* preset_data) {
     //load config
     furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
     cc1101_reset(&furi_hal_spi_bus_handle_subghz);
@@ -157,7 +149,6 @@ void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
     //load pa table
     memcpy(&pa[0], &preset_data[i + 2], 8);
     furi_hal_subghz_load_patable(pa);
-    furi_hal_subghz.preset = FuriHalSubGhzPresetCustom;
 
     //show debug
     if(furi_hal_rtc_is_flag_set(FuriHalRtcFlagDebug)) {
@@ -173,7 +164,7 @@ void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
     }
 }
 
-void furi_hal_subghz_load_registers(uint8_t* data) {
+void furi_hal_subghz_load_registers(const uint8_t* data) {
     furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
     cc1101_reset(&furi_hal_spi_bus_handle_subghz);
     uint32_t i = 0;

firmware/targets/f7/furi_hal/furi_hal_subghz.h

@@ -5,6 +5,8 @@
 
 #pragma once
 
+#include <lib/subghz/devices/preset.h>
+
 #include <stdbool.h>
 #include <stdint.h>
 #include <stddef.h>
@@ -20,18 +22,6 @@ extern "C" {
 #define API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF (API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL / 2)
 #define API_HAL_SUBGHZ_ASYNC_TX_GUARD_TIME 999
 
-/** Radio Presets */
-typedef enum {
-    FuriHalSubGhzPresetIDLE, /**< default configuration */
-    FuriHalSubGhzPresetOok270Async, /**< OOK, bandwidth 270kHz, asynchronous */
-    FuriHalSubGhzPresetOok650Async, /**< OOK, bandwidth 650kHz, asynchronous */
-    FuriHalSubGhzPreset2FSKDev238Async, /**< FM, deviation 2.380371 kHz, asynchronous */
-    FuriHalSubGhzPreset2FSKDev476Async, /**< FM, deviation 47.60742 kHz, asynchronous */
-    FuriHalSubGhzPresetMSK99_97KbAsync, /**< MSK, deviation 47.60742 kHz, 99.97Kb/s, asynchronous */
-    FuriHalSubGhzPresetGFSK9_99KbAsync, /**< GFSK, deviation 19.042969 kHz, 9.996Kb/s, asynchronous */
-    FuriHalSubGhzPresetCustom, /**Custom Preset*/
-} FuriHalSubGhzPreset;
-
 /** Switchable Radio Paths */
 typedef enum {
     FuriHalSubGhzPathIsolate, /**< Isolate Radio from antenna */
@@ -40,27 +30,6 @@ typedef enum {
     FuriHalSubGhzPath868, /**< Center Frequency: 868MHz. Path 3: SW1RF3-SW2RF3, LCLC */
 } FuriHalSubGhzPath;
 
-/** SubGhz state */
-typedef enum {
-    SubGhzStateInit, /**< Init pending */
-
-    SubGhzStateIdle, /**< Idle, energy save mode */
-
-    SubGhzStateAsyncRx, /**< Async RX started */
-
-    SubGhzStateAsyncTx, /**< Async TX started, DMA and timer is on */
-    SubGhzStateAsyncTxLast, /**< Async TX continue, DMA completed and timer got last value to go */
-    SubGhzStateAsyncTxEnd, /**< Async TX complete, cleanup needed */
-
-} SubGhzState;
-
-/** SubGhz regulation, receive transmission on the current frequency for the
- * region */
-typedef enum {
-    SubGhzRegulationOnlyRx, /**only Rx*/
-    SubGhzRegulationTxRx, /**TxRx*/
-} SubGhzRegulation;
-
 /* Mirror RX/TX async modulation signal to specified pin
  *
  * @warning    Configures pin to output mode. Make sure it is not connected
@@ -70,6 +39,12 @@ typedef enum {
  */
 void furi_hal_subghz_set_async_mirror_pin(const GpioPin* pin);
 
+/** Get data GPIO
+ *
+ * @return     pointer to the gpio pin structure
+ */
+const GpioPin* furi_hal_subghz_get_data_gpio();
+
 /** Initialize and switch to power save mode Used by internal API-HAL
  * initialization routine Can be used to reinitialize device to safe state and
  * send it to sleep
@@ -84,23 +59,17 @@ void furi_hal_subghz_sleep();
  */
 void furi_hal_subghz_dump_state();
 
-/** Load registers from preset by preset name
- *
- * @param      preset  to load
- */
-void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset);
-
 /** Load custom registers from preset
  *
  * @param      preset_data   registers to load
  */
-void furi_hal_subghz_load_custom_preset(uint8_t* preset_data);
+void furi_hal_subghz_load_custom_preset(const uint8_t* preset_data);
 
 /** Load registers
  *
  * @param      data  Registers data
  */
-void furi_hal_subghz_load_registers(uint8_t* data);
+void furi_hal_subghz_load_registers(const uint8_t* data);
 
 /** Load PATABLE
  *

firmware/targets/f7/furi_hal/furi_hal_subghz_configs.h

@@ -1,314 +0,0 @@
-#pragma once
-
-#include <cc1101.h>
-
-static const uint8_t furi_hal_subghz_preset_ook_270khz_async_regs[][2] = {
-    // https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
-
-    /* GPIO GD0 */
-    {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
-
-    /* FIFO and internals */
-    {CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
-
-    /* Packet engine */
-    {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
-
-    /* Frequency Synthesizer Control */
-    {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
-
-    // Modem Configuration
-    {CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
-    {CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
-    {CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
-    {CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
-    {CC1101_MDMCFG4, 0x67}, // Rx BW filter is 270.833333kHz
-
-    /* Main Radio Control State Machine */
-    {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
-
-    /* Frequency Offset Compensation Configuration */
-    {CC1101_FOCCFG,
-     0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
-
-    /* Automatic Gain Control */
-    {CC1101_AGCCTRL0,
-     0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
-    {CC1101_AGCCTRL1,
-     0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
-    {CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
-
-    /* Wake on radio and timeouts control */
-    {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
-
-    /* Frontend configuration */
-    {CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
-    {CC1101_FREND1, 0xB6}, //
-
-    /* End  */
-    {0, 0},
-};
-
-static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
-    // https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
-
-    /* GPIO GD0 */
-    {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
-
-    /* FIFO and internals */
-    {CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
-
-    /* Packet engine */
-    {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
-
-    /* Frequency Synthesizer Control */
-    {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
-
-    // Modem Configuration
-    {CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
-    {CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
-    {CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
-    {CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
-    {CC1101_MDMCFG4, 0x17}, // Rx BW filter is 650.000kHz
-
-    /* Main Radio Control State Machine */
-    {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
-
-    /* Frequency Offset Compensation Configuration */
-    {CC1101_FOCCFG,
-     0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
-
-    /* Automatic Gain Control */
-    // {CC1101_AGCTRL0,0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
-    // {CC1101_AGCTRL1,0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
-    // {CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
-    //MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
-    {CC1101_AGCCTRL0,
-     0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
-    {CC1101_AGCCTRL1,
-     0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
-    {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
-
-    /* Wake on radio and timeouts control */
-    {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
-
-    /* Frontend configuration */
-    {CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
-    {CC1101_FREND1, 0xB6}, //
-
-    /* End  */
-    {0, 0},
-};
-
-static const uint8_t furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs[][2] = {
-
-    /* GPIO GD0 */
-    {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
-
-    /* Frequency Synthesizer Control */
-    {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
-
-    /* Packet engine */
-    {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
-    {CC1101_PKTCTRL1, 0x04},
-
-    // // Modem Configuration
-    {CC1101_MDMCFG0, 0x00},
-    {CC1101_MDMCFG1, 0x02},
-    {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
-    {CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
-    {CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
-    {CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
-
-    /* Main Radio Control State Machine */
-    {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
-
-    /* Frequency Offset Compensation Configuration */
-    {CC1101_FOCCFG,
-     0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
-
-    /* Automatic Gain Control */
-    {CC1101_AGCCTRL0,
-     0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
-    {CC1101_AGCCTRL1,
-     0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
-    {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
-
-    /* Wake on radio and timeouts control */
-    {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
-
-    /* Frontend configuration */
-    {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
-    {CC1101_FREND1, 0x56},
-
-    /* End  */
-    {0, 0},
-};
-
-static const uint8_t furi_hal_subghz_preset_2fsk_dev47_6khz_async_regs[][2] = {
-
-    /* GPIO GD0 */
-    {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
-
-    /* Frequency Synthesizer Control */
-    {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
-
-    /* Packet engine */
-    {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
-    {CC1101_PKTCTRL1, 0x04},
-
-    // // Modem Configuration
-    {CC1101_MDMCFG0, 0x00},
-    {CC1101_MDMCFG1, 0x02},
-    {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
-    {CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
-    {CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
-    {CC1101_DEVIATN, 0x47}, //Deviation 47.60742 kHz
-
-    /* Main Radio Control State Machine */
-    {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
-
-    /* Frequency Offset Compensation Configuration */
-    {CC1101_FOCCFG,
-     0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
-
-    /* Automatic Gain Control */
-    {CC1101_AGCCTRL0,
-     0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
-    {CC1101_AGCCTRL1,
-     0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
-    {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
-
-    /* Wake on radio and timeouts control */
-    {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
-
-    /* Frontend configuration */
-    {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
-    {CC1101_FREND1, 0x56},
-
-    /* End  */
-    {0, 0},
-};
-
-static const uint8_t furi_hal_subghz_preset_msk_99_97kb_async_regs[][2] = {
-    /* GPIO GD0 */
-    {CC1101_IOCFG0, 0x06},
-
-    {CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
-    {CC1101_SYNC1, 0x46},
-    {CC1101_SYNC0, 0x4C},
-    {CC1101_ADDR, 0x00},
-    {CC1101_PKTLEN, 0x00},
-    {CC1101_CHANNR, 0x00},
-
-    {CC1101_PKTCTRL0, 0x05},
-
-    {CC1101_FSCTRL0, 0x23},
-    {CC1101_FSCTRL1, 0x06},
-
-    {CC1101_MDMCFG0, 0xF8},
-    {CC1101_MDMCFG1, 0x22},
-    {CC1101_MDMCFG2, 0x72},
-    {CC1101_MDMCFG3, 0xF8},
-    {CC1101_MDMCFG4, 0x5B},
-    {CC1101_DEVIATN, 0x47},
-
-    {CC1101_MCSM0, 0x18},
-    {CC1101_FOCCFG, 0x16},
-
-    {CC1101_AGCCTRL0, 0xB2},
-    {CC1101_AGCCTRL1, 0x00},
-    {CC1101_AGCCTRL2, 0xC7},
-
-    {CC1101_FREND0, 0x10},
-    {CC1101_FREND1, 0x56},
-
-    {CC1101_BSCFG, 0x1C},
-    {CC1101_FSTEST, 0x59},
-
-    /* End  */
-    {0, 0},
-};
-
-static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
-
-    {CC1101_IOCFG0, 0x06}, //GDO0 Output Pin Configuration
-    {CC1101_FIFOTHR, 0x47}, //RX FIFO and TX FIFO Thresholds
-
-    //1 : CRC calculation in TX and CRC check in RX enabled,
-    //1 : Variable packet length mode. Packet length configured by the first byte after sync word
-    {CC1101_PKTCTRL0, 0x05},
-
-    {CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control
-
-    {CC1101_SYNC1, 0x46},
-    {CC1101_SYNC0, 0x4C},
-    {CC1101_ADDR, 0x00},
-    {CC1101_PKTLEN, 0x00},
-
-    {CC1101_MDMCFG4, 0xC8}, //Modem Configuration 9.99
-    {CC1101_MDMCFG3, 0x93}, //Modem Configuration
-    {CC1101_MDMCFG2, 0x12}, // 2: 16/16 sync word bits detected
-
-    {CC1101_DEVIATN, 0x34}, //Deviation = 19.042969
-    {CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
-    {CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration
-
-    {CC1101_AGCCTRL2, 0x43}, //AGC Control
-    {CC1101_AGCCTRL1, 0x40},
-    {CC1101_AGCCTRL0, 0x91},
-
-    {CC1101_WORCTRL, 0xFB}, //Wake On Radio Control
-    /* End  */
-    {0, 0},
-};
-
-static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
-    0x00,
-    0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00};
-
-static const uint8_t furi_hal_subghz_preset_ook_async_patable_au[8] = {
-    0x00,
-    0x37, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00};
-
-static const uint8_t furi_hal_subghz_preset_2fsk_async_patable[8] = {
-    0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00};
-
-static const uint8_t furi_hal_subghz_preset_msk_async_patable[8] = {
-    0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00};
-
-static const uint8_t furi_hal_subghz_preset_gfsk_async_patable[8] = {
-    0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00};

firmware/targets/f7/platform_specific/intrinsic_export.h

@@ -1,10 +1,12 @@
 #include <errno.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 void __clear_cache(void*, void*);
+void* __aeabi_uldivmod(uint64_t, uint64_t);
 
 #ifdef __cplusplus
 }