mirror of
https://github.com/Next-Flip/Momentum-Firmware.git
synced 2026-05-13 16:28:36 -07:00
[FL-3375] SubGhz: add CC1101 module external (#2747)
* SubGhz: add CC1101 Ext driver * SubGhz: move TIM2 -> TIM17 use cc1101_ext * FuriHal: SPI move channel DMA 3,4 -> 6.7 * Documentation: fix font * SubGhz: add work with SubGhz devices by link to device * SubGhz: add support switching external/internal cc1101 "subghz chat" * SubGhz: add support switching external/internal cc1101 "subghz tx" and "subghz rx" * SubGhz: add "Radio Settings" scene * SubGhz: add icon * SubGhz: add supported CC1101 external module in SubGhz app * SubGhz: fix check frequency supported radio device * SubGhz: fix clang-formatted * Sughz: move dirver CC1101_Ext to lib , compile cmd ./fbt launch_app APPSRC=radio_device_cc1101_ext * SubGhz: fix CLI * SubGhz: fix PVS * SubGhz: delete comments * SubGhz: fix unit_test * Format sources * Update api symbols and drivers targets * Drivers: find proper place for target option * SubGhz: external device connected method naming * Format sources * SubGhz: fix module selection menu, when external is not connected * SubGhz: fix furi_assert(device); * SubGhz: fix split h and c * SubGhz: furi_hal_subghz remove preset load function by name * SubGhz: deleted comments * Format Sources * SubGhz: add some consts and fix unit tests * Sync API Symbols Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
This commit is contained in:
Skorpionm
@@ -12,10 +12,10 @@
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#define TAG "FuriHalSpi"
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#define SPI_DMA DMA2
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#define SPI_DMA_RX_CHANNEL LL_DMA_CHANNEL_3
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#define SPI_DMA_TX_CHANNEL LL_DMA_CHANNEL_4
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#define SPI_DMA_RX_IRQ FuriHalInterruptIdDma2Ch3
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#define SPI_DMA_TX_IRQ FuriHalInterruptIdDma2Ch4
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#define SPI_DMA_RX_CHANNEL LL_DMA_CHANNEL_6
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#define SPI_DMA_TX_CHANNEL LL_DMA_CHANNEL_7
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#define SPI_DMA_RX_IRQ FuriHalInterruptIdDma2Ch6
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#define SPI_DMA_TX_IRQ FuriHalInterruptIdDma2Ch7
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#define SPI_DMA_RX_DEF SPI_DMA, SPI_DMA_RX_CHANNEL
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#define SPI_DMA_TX_DEF SPI_DMA, SPI_DMA_TX_CHANNEL
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@@ -170,18 +170,18 @@ bool furi_hal_spi_bus_trx(
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}
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static void spi_dma_isr() {
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#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_3
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if(LL_DMA_IsActiveFlag_TC3(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_RX_DEF)) {
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LL_DMA_ClearFlag_TC3(SPI_DMA);
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#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_6
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if(LL_DMA_IsActiveFlag_TC6(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_RX_DEF)) {
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LL_DMA_ClearFlag_TC6(SPI_DMA);
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furi_check(furi_semaphore_release(spi_dma_completed) == FuriStatusOk);
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}
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#else
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#error Update this code. Would you kindly?
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#endif
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#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_4
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if(LL_DMA_IsActiveFlag_TC4(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_TX_DEF)) {
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LL_DMA_ClearFlag_TC4(SPI_DMA);
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#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_7
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if(LL_DMA_IsActiveFlag_TC7(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_TX_DEF)) {
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LL_DMA_ClearFlag_TC7(SPI_DMA);
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furi_check(furi_semaphore_release(spi_dma_completed) == FuriStatusOk);
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}
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#else
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@@ -241,8 +241,8 @@ bool furi_hal_spi_bus_trx_dma(
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dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
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LL_DMA_Init(SPI_DMA_TX_DEF, &dma_config);
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#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_4
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LL_DMA_ClearFlag_TC4(SPI_DMA);
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#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_7
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LL_DMA_ClearFlag_TC7(SPI_DMA);
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#else
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#error Update this code. Would you kindly?
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#endif
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@@ -315,8 +315,8 @@ bool furi_hal_spi_bus_trx_dma(
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dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
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LL_DMA_Init(SPI_DMA_RX_DEF, &dma_config);
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#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_3
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LL_DMA_ClearFlag_TC3(SPI_DMA);
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#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_6
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LL_DMA_ClearFlag_TC6(SPI_DMA);
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#else
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#error Update this code. Would you kindly?
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#endif
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@@ -1,6 +1,5 @@
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#include <furi_hal_subghz.h>
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#include <furi_hal_subghz_configs.h>
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#include <lib/subghz/devices/cc1101_configs.h>
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#include <furi_hal_region.h>
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#include <furi_hal_version.h>
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#include <furi_hal_rtc.h>
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@@ -27,17 +26,36 @@ static uint32_t furi_hal_subghz_debug_gpio_buff[2];
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#define SUBGHZ_DMA_CH1_DEF SUBGHZ_DMA, SUBGHZ_DMA_CH1_CHANNEL
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#define SUBGHZ_DMA_CH2_DEF SUBGHZ_DMA, SUBGHZ_DMA_CH2_CHANNEL
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/** SubGhz state */
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typedef enum {
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SubGhzStateInit, /**< Init pending */
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SubGhzStateIdle, /**< Idle, energy save mode */
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SubGhzStateAsyncRx, /**< Async RX started */
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SubGhzStateAsyncTx, /**< Async TX started, DMA and timer is on */
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SubGhzStateAsyncTxLast, /**< Async TX continue, DMA completed and timer got last value to go */
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SubGhzStateAsyncTxEnd, /**< Async TX complete, cleanup needed */
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} SubGhzState;
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/** SubGhz regulation, receive transmission on the current frequency for the
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* region */
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typedef enum {
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SubGhzRegulationOnlyRx, /**only Rx*/
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SubGhzRegulationTxRx, /**TxRx*/
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} SubGhzRegulation;
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typedef struct {
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volatile SubGhzState state;
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volatile SubGhzRegulation regulation;
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volatile FuriHalSubGhzPreset preset;
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const GpioPin* async_mirror_pin;
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} FuriHalSubGhz;
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volatile FuriHalSubGhz furi_hal_subghz = {
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.state = SubGhzStateInit,
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.regulation = SubGhzRegulationTxRx,
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.preset = FuriHalSubGhzPresetIDLE,
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.async_mirror_pin = NULL,
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};
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@@ -45,10 +63,13 @@ void furi_hal_subghz_set_async_mirror_pin(const GpioPin* pin) {
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furi_hal_subghz.async_mirror_pin = pin;
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}
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const GpioPin* furi_hal_subghz_get_data_gpio() {
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return &gpio_cc1101_g0;
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}
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void furi_hal_subghz_init() {
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furi_assert(furi_hal_subghz.state == SubGhzStateInit);
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furi_hal_subghz.state = SubGhzStateIdle;
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furi_hal_subghz.preset = FuriHalSubGhzPresetIDLE;
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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@@ -102,8 +123,6 @@ void furi_hal_subghz_sleep() {
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cc1101_shutdown(&furi_hal_spi_bus_handle_subghz);
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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furi_hal_subghz.preset = FuriHalSubGhzPresetIDLE;
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}
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void furi_hal_subghz_dump_state() {
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@@ -115,34 +134,7 @@ void furi_hal_subghz_dump_state() {
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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}
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void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
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if(preset == FuriHalSubGhzPresetOok650Async) {
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furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_ook_650khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
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} else if(preset == FuriHalSubGhzPresetOok270Async) {
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furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_ook_270khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
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} else if(preset == FuriHalSubGhzPreset2FSKDev238Async) {
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furi_hal_subghz_load_registers(
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(uint8_t*)furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
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} else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
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furi_hal_subghz_load_registers(
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(uint8_t*)furi_hal_subghz_preset_2fsk_dev47_6khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
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} else if(preset == FuriHalSubGhzPresetMSK99_97KbAsync) {
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furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_msk_99_97kb_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_msk_async_patable);
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} else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
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furi_hal_subghz_load_registers((uint8_t*)furi_hal_subghz_preset_gfsk_9_99kb_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_gfsk_async_patable);
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} else {
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furi_crash("SubGhz: Missing config.");
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}
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furi_hal_subghz.preset = preset;
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}
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void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
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void furi_hal_subghz_load_custom_preset(const uint8_t* preset_data) {
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//load config
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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cc1101_reset(&furi_hal_spi_bus_handle_subghz);
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@@ -157,7 +149,6 @@ void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
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//load pa table
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memcpy(&pa[0], &preset_data[i + 2], 8);
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furi_hal_subghz_load_patable(pa);
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furi_hal_subghz.preset = FuriHalSubGhzPresetCustom;
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//show debug
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if(furi_hal_rtc_is_flag_set(FuriHalRtcFlagDebug)) {
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@@ -173,7 +164,7 @@ void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
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}
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}
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void furi_hal_subghz_load_registers(uint8_t* data) {
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void furi_hal_subghz_load_registers(const uint8_t* data) {
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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cc1101_reset(&furi_hal_spi_bus_handle_subghz);
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uint32_t i = 0;
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@@ -5,6 +5,8 @@
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#pragma once
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#include <lib/subghz/devices/preset.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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@@ -20,18 +22,6 @@ extern "C" {
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#define API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF (API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL / 2)
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#define API_HAL_SUBGHZ_ASYNC_TX_GUARD_TIME 999
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/** Radio Presets */
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typedef enum {
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FuriHalSubGhzPresetIDLE, /**< default configuration */
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FuriHalSubGhzPresetOok270Async, /**< OOK, bandwidth 270kHz, asynchronous */
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FuriHalSubGhzPresetOok650Async, /**< OOK, bandwidth 650kHz, asynchronous */
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FuriHalSubGhzPreset2FSKDev238Async, /**< FM, deviation 2.380371 kHz, asynchronous */
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FuriHalSubGhzPreset2FSKDev476Async, /**< FM, deviation 47.60742 kHz, asynchronous */
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FuriHalSubGhzPresetMSK99_97KbAsync, /**< MSK, deviation 47.60742 kHz, 99.97Kb/s, asynchronous */
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FuriHalSubGhzPresetGFSK9_99KbAsync, /**< GFSK, deviation 19.042969 kHz, 9.996Kb/s, asynchronous */
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FuriHalSubGhzPresetCustom, /**Custom Preset*/
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} FuriHalSubGhzPreset;
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/** Switchable Radio Paths */
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typedef enum {
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FuriHalSubGhzPathIsolate, /**< Isolate Radio from antenna */
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@@ -40,27 +30,6 @@ typedef enum {
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FuriHalSubGhzPath868, /**< Center Frequency: 868MHz. Path 3: SW1RF3-SW2RF3, LCLC */
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} FuriHalSubGhzPath;
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/** SubGhz state */
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typedef enum {
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SubGhzStateInit, /**< Init pending */
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SubGhzStateIdle, /**< Idle, energy save mode */
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SubGhzStateAsyncRx, /**< Async RX started */
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SubGhzStateAsyncTx, /**< Async TX started, DMA and timer is on */
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SubGhzStateAsyncTxLast, /**< Async TX continue, DMA completed and timer got last value to go */
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SubGhzStateAsyncTxEnd, /**< Async TX complete, cleanup needed */
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} SubGhzState;
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/** SubGhz regulation, receive transmission on the current frequency for the
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* region */
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typedef enum {
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SubGhzRegulationOnlyRx, /**only Rx*/
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SubGhzRegulationTxRx, /**TxRx*/
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} SubGhzRegulation;
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/* Mirror RX/TX async modulation signal to specified pin
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*
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* @warning Configures pin to output mode. Make sure it is not connected
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@@ -70,6 +39,12 @@ typedef enum {
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*/
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void furi_hal_subghz_set_async_mirror_pin(const GpioPin* pin);
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/** Get data GPIO
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*
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* @return pointer to the gpio pin structure
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*/
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const GpioPin* furi_hal_subghz_get_data_gpio();
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/** Initialize and switch to power save mode Used by internal API-HAL
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* initialization routine Can be used to reinitialize device to safe state and
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* send it to sleep
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@@ -84,23 +59,17 @@ void furi_hal_subghz_sleep();
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*/
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void furi_hal_subghz_dump_state();
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/** Load registers from preset by preset name
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*
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* @param preset to load
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*/
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void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset);
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/** Load custom registers from preset
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*
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* @param preset_data registers to load
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*/
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void furi_hal_subghz_load_custom_preset(uint8_t* preset_data);
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void furi_hal_subghz_load_custom_preset(const uint8_t* preset_data);
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/** Load registers
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*
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* @param data Registers data
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*/
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void furi_hal_subghz_load_registers(uint8_t* data);
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void furi_hal_subghz_load_registers(const uint8_t* data);
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/** Load PATABLE
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*
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@@ -1,314 +0,0 @@
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#pragma once
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#include <cc1101.h>
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static const uint8_t furi_hal_subghz_preset_ook_270khz_async_regs[][2] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
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{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
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{CC1101_MDMCFG4, 0x67}, // Rx BW filter is 270.833333kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
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{CC1101_FREND1, 0xB6}, //
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/* End */
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{0, 0},
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};
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static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
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||||
{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
|
||||
{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
|
||||
{CC1101_MDMCFG4, 0x17}, // Rx BW filter is 650.000kHz
|
||||
|
||||
/* Main Radio Control State Machine */
|
||||
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
|
||||
|
||||
/* Frequency Offset Compensation Configuration */
|
||||
{CC1101_FOCCFG,
|
||||
0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
|
||||
|
||||
/* Automatic Gain Control */
|
||||
// {CC1101_AGCTRL0,0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
|
||||
// {CC1101_AGCTRL1,0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
|
||||
// {CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
|
||||
//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
|
||||
{CC1101_AGCCTRL0,
|
||||
0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
|
||||
{CC1101_AGCCTRL1,
|
||||
0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
|
||||
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
|
||||
|
||||
/* Wake on radio and timeouts control */
|
||||
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
|
||||
|
||||
/* Frontend configuration */
|
||||
{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
|
||||
{CC1101_FREND1, 0xB6}, //
|
||||
|
||||
/* End */
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs[][2] = {
|
||||
|
||||
/* GPIO GD0 */
|
||||
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
|
||||
|
||||
/* Frequency Synthesizer Control */
|
||||
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
|
||||
|
||||
/* Packet engine */
|
||||
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
|
||||
{CC1101_PKTCTRL1, 0x04},
|
||||
|
||||
// // Modem Configuration
|
||||
{CC1101_MDMCFG0, 0x00},
|
||||
{CC1101_MDMCFG1, 0x02},
|
||||
{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
|
||||
{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
|
||||
{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
|
||||
{CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
|
||||
|
||||
/* Main Radio Control State Machine */
|
||||
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
|
||||
|
||||
/* Frequency Offset Compensation Configuration */
|
||||
{CC1101_FOCCFG,
|
||||
0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
|
||||
|
||||
/* Automatic Gain Control */
|
||||
{CC1101_AGCCTRL0,
|
||||
0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
|
||||
{CC1101_AGCCTRL1,
|
||||
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
|
||||
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
|
||||
|
||||
/* Wake on radio and timeouts control */
|
||||
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
|
||||
|
||||
/* Frontend configuration */
|
||||
{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
|
||||
{CC1101_FREND1, 0x56},
|
||||
|
||||
/* End */
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_2fsk_dev47_6khz_async_regs[][2] = {
|
||||
|
||||
/* GPIO GD0 */
|
||||
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
|
||||
|
||||
/* Frequency Synthesizer Control */
|
||||
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
|
||||
|
||||
/* Packet engine */
|
||||
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
|
||||
{CC1101_PKTCTRL1, 0x04},
|
||||
|
||||
// // Modem Configuration
|
||||
{CC1101_MDMCFG0, 0x00},
|
||||
{CC1101_MDMCFG1, 0x02},
|
||||
{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
|
||||
{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
|
||||
{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
|
||||
{CC1101_DEVIATN, 0x47}, //Deviation 47.60742 kHz
|
||||
|
||||
/* Main Radio Control State Machine */
|
||||
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
|
||||
|
||||
/* Frequency Offset Compensation Configuration */
|
||||
{CC1101_FOCCFG,
|
||||
0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
|
||||
|
||||
/* Automatic Gain Control */
|
||||
{CC1101_AGCCTRL0,
|
||||
0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
|
||||
{CC1101_AGCCTRL1,
|
||||
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
|
||||
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
|
||||
|
||||
/* Wake on radio and timeouts control */
|
||||
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
|
||||
|
||||
/* Frontend configuration */
|
||||
{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
|
||||
{CC1101_FREND1, 0x56},
|
||||
|
||||
/* End */
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_msk_99_97kb_async_regs[][2] = {
|
||||
/* GPIO GD0 */
|
||||
{CC1101_IOCFG0, 0x06},
|
||||
|
||||
{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
|
||||
{CC1101_SYNC1, 0x46},
|
||||
{CC1101_SYNC0, 0x4C},
|
||||
{CC1101_ADDR, 0x00},
|
||||
{CC1101_PKTLEN, 0x00},
|
||||
{CC1101_CHANNR, 0x00},
|
||||
|
||||
{CC1101_PKTCTRL0, 0x05},
|
||||
|
||||
{CC1101_FSCTRL0, 0x23},
|
||||
{CC1101_FSCTRL1, 0x06},
|
||||
|
||||
{CC1101_MDMCFG0, 0xF8},
|
||||
{CC1101_MDMCFG1, 0x22},
|
||||
{CC1101_MDMCFG2, 0x72},
|
||||
{CC1101_MDMCFG3, 0xF8},
|
||||
{CC1101_MDMCFG4, 0x5B},
|
||||
{CC1101_DEVIATN, 0x47},
|
||||
|
||||
{CC1101_MCSM0, 0x18},
|
||||
{CC1101_FOCCFG, 0x16},
|
||||
|
||||
{CC1101_AGCCTRL0, 0xB2},
|
||||
{CC1101_AGCCTRL1, 0x00},
|
||||
{CC1101_AGCCTRL2, 0xC7},
|
||||
|
||||
{CC1101_FREND0, 0x10},
|
||||
{CC1101_FREND1, 0x56},
|
||||
|
||||
{CC1101_BSCFG, 0x1C},
|
||||
{CC1101_FSTEST, 0x59},
|
||||
|
||||
/* End */
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
|
||||
|
||||
{CC1101_IOCFG0, 0x06}, //GDO0 Output Pin Configuration
|
||||
{CC1101_FIFOTHR, 0x47}, //RX FIFO and TX FIFO Thresholds
|
||||
|
||||
//1 : CRC calculation in TX and CRC check in RX enabled,
|
||||
//1 : Variable packet length mode. Packet length configured by the first byte after sync word
|
||||
{CC1101_PKTCTRL0, 0x05},
|
||||
|
||||
{CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control
|
||||
|
||||
{CC1101_SYNC1, 0x46},
|
||||
{CC1101_SYNC0, 0x4C},
|
||||
{CC1101_ADDR, 0x00},
|
||||
{CC1101_PKTLEN, 0x00},
|
||||
|
||||
{CC1101_MDMCFG4, 0xC8}, //Modem Configuration 9.99
|
||||
{CC1101_MDMCFG3, 0x93}, //Modem Configuration
|
||||
{CC1101_MDMCFG2, 0x12}, // 2: 16/16 sync word bits detected
|
||||
|
||||
{CC1101_DEVIATN, 0x34}, //Deviation = 19.042969
|
||||
{CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
|
||||
{CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration
|
||||
|
||||
{CC1101_AGCCTRL2, 0x43}, //AGC Control
|
||||
{CC1101_AGCCTRL1, 0x40},
|
||||
{CC1101_AGCCTRL0, 0x91},
|
||||
|
||||
{CC1101_WORCTRL, 0xFB}, //Wake On Radio Control
|
||||
/* End */
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
|
||||
0x00,
|
||||
0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_ook_async_patable_au[8] = {
|
||||
0x00,
|
||||
0x37, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_2fsk_async_patable[8] = {
|
||||
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_msk_async_patable[8] = {
|
||||
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
|
||||
static const uint8_t furi_hal_subghz_preset_gfsk_async_patable[8] = {
|
||||
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
Reference in New Issue
Block a user