mirror of
https://github.com/Next-Flip/Momentum-Firmware.git
synced 2026-04-24 03:29:57 -07:00
NFC refactoring (#3050)
"A long time ago in a galaxy far, far away...." we started NFC subsystem refactoring. Starring: - @gornekich - NFC refactoring project lead, architect, senior developer - @gsurkov - architect, senior developer - @RebornedBrain - senior developer Supporting roles: - @skotopes, @DrZlo13, @hedger - general architecture advisors, code review - @Astrrra, @doomwastaken, @Hellitron, @ImagineVagon333 - quality assurance Special thanks: @bettse, @pcunning, @nxv, @noproto, @AloneLiberty and everyone else who has been helping us all this time and contributing valuable knowledges, ideas and source code.
This commit is contained in:
gornekich
81
lib/drivers/st25r3916.c
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81
lib/drivers/st25r3916.c
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@@ -0,0 +1,81 @@
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#include "st25r3916.h"
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#include <furi.h>
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void st25r3916_mask_irq(FuriHalSpiBusHandle* handle, uint32_t mask) {
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furi_assert(handle);
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uint8_t irq_mask_regs[4] = {
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mask & 0xff,
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(mask >> 8) & 0xff,
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(mask >> 16) & 0xff,
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(mask >> 24) & 0xff,
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};
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st25r3916_write_burst_regs(handle, ST25R3916_REG_IRQ_MASK_MAIN, irq_mask_regs, 4);
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}
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uint32_t st25r3916_get_irq(FuriHalSpiBusHandle* handle) {
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furi_assert(handle);
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uint8_t irq_regs[4] = {};
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uint32_t irq = 0;
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st25r3916_read_burst_regs(handle, ST25R3916_REG_IRQ_MASK_MAIN, irq_regs, 4);
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// FURI_LOG_I(
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// "Mask Irq", "%02X %02X %02X %02X", irq_regs[0], irq_regs[1], irq_regs[2], irq_regs[3]);
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st25r3916_read_burst_regs(handle, ST25R3916_REG_IRQ_MAIN, irq_regs, 4);
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irq = (uint32_t)irq_regs[0];
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irq |= (uint32_t)irq_regs[1] << 8;
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irq |= (uint32_t)irq_regs[2] << 16;
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irq |= (uint32_t)irq_regs[3] << 24;
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// FURI_LOG_I("iRQ", "%02X %02X %02X %02X", irq_regs[0], irq_regs[1], irq_regs[2], irq_regs[3]);
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return irq;
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}
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void st25r3916_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* buff, size_t bits) {
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furi_assert(handle);
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furi_assert(buff);
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size_t bytes = (bits + 7) / 8;
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st25r3916_write_reg(handle, ST25R3916_REG_NUM_TX_BYTES2, (uint8_t)(bits & 0xFFU));
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st25r3916_write_reg(handle, ST25R3916_REG_NUM_TX_BYTES1, (uint8_t)((bits >> 8) & 0xFFU));
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st25r3916_reg_write_fifo(handle, buff, bytes);
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}
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bool st25r3916_read_fifo(
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FuriHalSpiBusHandle* handle,
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uint8_t* buff,
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size_t buff_size,
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size_t* buff_bits) {
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furi_assert(handle);
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furi_assert(buff);
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bool read_success = false;
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do {
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uint8_t fifo_status[2] = {};
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st25r3916_read_burst_regs(handle, ST25R3916_REG_FIFO_STATUS1, fifo_status, 2);
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size_t bytes = ((fifo_status[1] & ST25R3916_REG_FIFO_STATUS2_fifo_b_mask) >>
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ST25R3916_REG_FIFO_STATUS2_fifo_b_shift) |
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fifo_status[0];
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uint8_t bits =
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((fifo_status[1] & ST25R3916_REG_FIFO_STATUS2_fifo_lb_mask) >>
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ST25R3916_REG_FIFO_STATUS2_fifo_lb_shift);
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if(bytes == 0) break;
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if(bytes > buff_size) break;
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st25r3916_reg_read_fifo(handle, buff, bytes);
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if(bits) {
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*buff_bits = (bytes - 1) * 8 + bits;
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} else {
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*buff_bits = bytes * 8;
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}
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read_success = true;
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} while(false);
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return read_success;
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}
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113
lib/drivers/st25r3916.h
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113
lib/drivers/st25r3916.h
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@@ -0,0 +1,113 @@
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#pragma once
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#include "st25r3916_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ST25R3916_IRQ_MASK_ALL (uint32_t)(0xFFFFFFFFUL) /** All ST25R3916 interrupt sources */
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#define ST25R3916_IRQ_MASK_NONE (uint32_t)(0x00000000UL) /**No ST25R3916 interrupt source */
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/** Main interrupt register */
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#define ST25R3916_IRQ_MASK_OSC (uint32_t)(0x00000080U) /** ST25R3916 oscillator stable interrupt */
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#define ST25R3916_IRQ_MASK_FWL (uint32_t)(0x00000040U) /** ST25R3916 FIFO water level interrupt */
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#define ST25R3916_IRQ_MASK_RXS (uint32_t)(0x00000020U) /** ST25R3916 start of receive interrupt */
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#define ST25R3916_IRQ_MASK_RXE (uint32_t)(0x00000010U) /** ST25R3916 end of receive interrupt */
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#define ST25R3916_IRQ_MASK_TXE \
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(uint32_t)(0x00000008U) /** ST25R3916 end of transmission interrupt */
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#define ST25R3916_IRQ_MASK_COL (uint32_t)(0x00000004U) /** ST25R3916 bit collision interrupt */
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#define ST25R3916_IRQ_MASK_RX_REST \
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(uint32_t)(0x00000002U) /** ST25R3916 automatic reception restart interrupt */
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#define ST25R3916_IRQ_MASK_RFU (uint32_t)(0x00000001U) /** ST25R3916 RFU interrupt */
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/** Timer and NFC interrupt register */
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#define ST25R3916_IRQ_MASK_DCT \
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(uint32_t)(0x00008000U) /** ST25R3916 termination of direct command interrupt. */
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#define ST25R3916_IRQ_MASK_NRE \
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(uint32_t)(0x00004000U) /** ST25R3916 no-response timer expired interrupt */
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#define ST25R3916_IRQ_MASK_GPE \
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(uint32_t)(0x00002000U) /** ST25R3916 general purpose timer expired interrupt */
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#define ST25R3916_IRQ_MASK_EON (uint32_t)(0x00001000U) /** ST25R3916 external field on interrupt */
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#define ST25R3916_IRQ_MASK_EOF \
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(uint32_t)(0x00000800U) /** ST25R3916 external field off interrupt */
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#define ST25R3916_IRQ_MASK_CAC \
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(uint32_t)(0x00000400U) /** ST25R3916 collision during RF collision avoidance */
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#define ST25R3916_IRQ_MASK_CAT \
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(uint32_t)(0x00000200U) /** ST25R3916 minimum guard time expired interrupt */
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#define ST25R3916_IRQ_MASK_NFCT \
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(uint32_t)(0x00000100U) /** ST25R3916 initiator bit rate recognised interrupt */
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/** Error and wake-up interrupt register */
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#define ST25R3916_IRQ_MASK_CRC (uint32_t)(0x00800000U) /** ST25R3916 CRC error interrupt */
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#define ST25R3916_IRQ_MASK_PAR (uint32_t)(0x00400000U) /** ST25R3916 parity error interrupt */
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#define ST25R3916_IRQ_MASK_ERR2 \
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(uint32_t)(0x00200000U) /** ST25R3916 soft framing error interrupt */
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#define ST25R3916_IRQ_MASK_ERR1 \
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(uint32_t)(0x00100000U) /** ST25R3916 hard framing error interrupt */
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#define ST25R3916_IRQ_MASK_WT (uint32_t)(0x00080000U) /** ST25R3916 wake-up interrupt */
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#define ST25R3916_IRQ_MASK_WAM \
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(uint32_t)(0x00040000U) /** ST25R3916 wake-up due to amplitude interrupt */
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#define ST25R3916_IRQ_MASK_WPH \
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(uint32_t)(0x00020000U) /** ST25R3916 wake-up due to phase interrupt */
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#define ST25R3916_IRQ_MASK_WCAP \
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(uint32_t)(0x00010000U) /** ST25R3916 wake-up due to capacitance measurement */
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/** Passive Target Interrupt Register */
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#define ST25R3916_IRQ_MASK_PPON2 \
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(uint32_t)(0x80000000U) /** ST25R3916 PPON2 Field on waiting Timer interrupt */
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#define ST25R3916_IRQ_MASK_SL_WL \
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(uint32_t)(0x40000000U) /** ST25R3916 Passive target slot number water level interrupt */
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#define ST25R3916_IRQ_MASK_APON \
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(uint32_t)(0x20000000U) /** ST25R3916 Anticollision done and Field On interrupt */
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#define ST25R3916_IRQ_MASK_RXE_PTA \
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(uint32_t)(0x10000000U) /** ST25R3916 RXE with an automatic response interrupt */
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#define ST25R3916_IRQ_MASK_WU_F \
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(uint32_t)(0x08000000U) /** ST25R3916 212/424b/s Passive target interrupt: Active */
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#define ST25R3916_IRQ_MASK_RFU2 (uint32_t)(0x04000000U) /** ST25R3916 RFU2 interrupt */
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#define ST25R3916_IRQ_MASK_WU_A_X \
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(uint32_t)(0x02000000U) /** ST25R3916 106kb/s Passive target state interrupt: Active* */
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#define ST25R3916_IRQ_MASK_WU_A \
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(uint32_t)(0x01000000U) /** ST25R3916 106kb/s Passive target state interrupt: Active */
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/** Mask st25r3916 interrupts
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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* @param mask - mask of interrupts to be disabled
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*/
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void st25r3916_mask_irq(FuriHalSpiBusHandle* handle, uint32_t mask);
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/** Get st25r3916 interrupts
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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*
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* @return received interrupts
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*/
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uint32_t st25r3916_get_irq(FuriHalSpiBusHandle* handle);
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/** Write FIFO
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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* @param buff - buffer to write to FIFO
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* @param bits - number of bits to write
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*/
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void st25r3916_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* buff, size_t bits);
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/** Read FIFO
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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* @param buff - buffer to read from FIFO
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* @param buff_size - buffer size n bytes
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* @param buff_bits - pointer to number of bits read
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*
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* @return true if read success, false otherwise
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*/
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bool st25r3916_read_fifo(
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FuriHalSpiBusHandle* handle,
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uint8_t* buff,
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size_t buff_size,
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size_t* buff_bits);
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#ifdef __cplusplus
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}
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#endif
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257
lib/drivers/st25r3916_reg.c
Normal file
257
lib/drivers/st25r3916_reg.c
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@@ -0,0 +1,257 @@
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#include "st25r3916_reg.h"
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#include <furi.h>
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#define ST25R3916_WRITE_MODE \
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(0U << 6) /*!< ST25R3916 Operation Mode: Write */
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#define ST25R3916_READ_MODE \
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(1U << 6) /*!< ST25R3916 Operation Mode: Read */
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#define ST25R3916_CMD_MODE \
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(3U << 6) /*!< ST25R3916 Operation Mode: Direct Command */
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#define ST25R3916_FIFO_LOAD \
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(0x80U) /*!< ST25R3916 Operation Mode: FIFO Load */
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#define ST25R3916_FIFO_READ \
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(0x9FU) /*!< ST25R3916 Operation Mode: FIFO Read */
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#define ST25R3916_PT_A_CONFIG_LOAD \
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(0xA0U) /*!< ST25R3916 Operation Mode: Passive Target Memory A-Config Load */
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#define ST25R3916_PT_F_CONFIG_LOAD \
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(0xA8U) /*!< ST25R3916 Operation Mode: Passive Target Memory F-Config Load */
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#define ST25R3916_PT_TSN_DATA_LOAD \
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(0xACU) /*!< ST25R3916 Operation Mode: Passive Target Memory TSN Load */
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#define ST25R3916_PT_MEM_READ \
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(0xBFU) /*!< ST25R3916 Operation Mode: Passive Target Memory Read */
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#define ST25R3916_CMD_LEN \
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(1U) /*!< ST25R3916 CMD length */
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#define ST25R3916_FIFO_DEPTH (512U)
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#define ST25R3916_BUF_LEN \
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(ST25R3916_CMD_LEN + \
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ST25R3916_FIFO_DEPTH) /*!< ST25R3916 communication buffer: CMD + FIFO length */
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static void st25r3916_reg_tx_byte(FuriHalSpiBusHandle* handle, uint8_t byte) {
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uint8_t val = byte;
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furi_hal_spi_bus_tx(handle, &val, 1, 5);
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}
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void st25r3916_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* val) {
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furi_assert(handle);
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st25r3916_read_burst_regs(handle, reg, val, 1);
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}
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void st25r3916_read_burst_regs(
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FuriHalSpiBusHandle* handle,
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uint8_t reg_start,
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uint8_t* values,
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uint8_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_assert(length);
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furi_hal_gpio_write(handle->cs, false);
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if(reg_start & ST25R3916_SPACE_B) {
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// Send direct command first
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st25r3916_reg_tx_byte(handle, ST25R3916_CMD_SPACE_B_ACCESS);
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}
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st25r3916_reg_tx_byte(handle, (reg_start & ~ST25R3916_SPACE_B) | ST25R3916_READ_MODE);
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furi_hal_spi_bus_rx(handle, values, length, 5);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t val) {
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furi_assert(handle);
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uint8_t reg_val = val;
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st25r3916_write_burst_regs(handle, reg, ®_val, 1);
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}
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void st25r3916_write_burst_regs(
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FuriHalSpiBusHandle* handle,
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uint8_t reg_start,
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const uint8_t* values,
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uint8_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_assert(length);
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furi_hal_gpio_write(handle->cs, false);
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if(reg_start & ST25R3916_SPACE_B) {
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// Send direct command first
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st25r3916_reg_tx_byte(handle, ST25R3916_CMD_SPACE_B_ACCESS);
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}
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st25r3916_reg_tx_byte(handle, (reg_start & ~ST25R3916_SPACE_B) | ST25R3916_WRITE_MODE);
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furi_hal_spi_bus_tx(handle, values, length, 5);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_reg_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_assert(length);
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furi_assert(length <= ST25R3916_FIFO_DEPTH);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_FIFO_LOAD);
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furi_hal_spi_bus_tx(handle, buff, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_reg_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_assert(length);
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furi_assert(length <= ST25R3916_FIFO_DEPTH);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_FIFO_READ);
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furi_hal_spi_bus_rx(handle, buff, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_pta_mem(FuriHalSpiBusHandle* handle, const uint8_t* values, size_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_assert(length);
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furi_assert(length <= ST25R3916_PTM_LEN);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_A_CONFIG_LOAD);
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furi_hal_spi_bus_tx(handle, values, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_read_pta_mem(FuriHalSpiBusHandle* handle, uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_assert(length);
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furi_assert(length <= ST25R3916_PTM_LEN);
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uint8_t tmp_buff[ST25R3916_PTM_LEN + 1];
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_MEM_READ);
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furi_hal_spi_bus_rx(handle, tmp_buff, length + 1, 200);
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furi_hal_gpio_write(handle->cs, true);
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memcpy(buff, tmp_buff + 1, length);
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}
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void st25r3916_write_ptf_mem(FuriHalSpiBusHandle* handle, const uint8_t* values, size_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_F_CONFIG_LOAD);
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furi_hal_spi_bus_tx(handle, values, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_pttsn_mem(FuriHalSpiBusHandle* handle, uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_TSN_DATA_LOAD);
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furi_hal_spi_bus_tx(handle, buff, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_direct_cmd(FuriHalSpiBusHandle* handle, uint8_t cmd) {
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furi_assert(handle);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, cmd | ST25R3916_CMD_MODE);
|
||||
furi_hal_gpio_write(handle->cs, true);
|
||||
}
|
||||
|
||||
void st25r3916_read_test_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* val) {
|
||||
furi_assert(handle);
|
||||
|
||||
furi_hal_gpio_write(handle->cs, false);
|
||||
st25r3916_reg_tx_byte(handle, ST25R3916_CMD_TEST_ACCESS);
|
||||
st25r3916_reg_tx_byte(handle, reg | ST25R3916_READ_MODE);
|
||||
furi_hal_spi_bus_rx(handle, val, 1, 5);
|
||||
furi_hal_gpio_write(handle->cs, true);
|
||||
}
|
||||
|
||||
void st25r3916_write_test_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t val) {
|
||||
furi_assert(handle);
|
||||
|
||||
furi_hal_gpio_write(handle->cs, false);
|
||||
st25r3916_reg_tx_byte(handle, ST25R3916_CMD_TEST_ACCESS);
|
||||
st25r3916_reg_tx_byte(handle, reg | ST25R3916_WRITE_MODE);
|
||||
furi_hal_spi_bus_tx(handle, &val, 1, 5);
|
||||
furi_hal_gpio_write(handle->cs, true);
|
||||
}
|
||||
|
||||
void st25r3916_clear_reg_bits(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t clr_mask) {
|
||||
furi_assert(handle);
|
||||
|
||||
uint8_t reg_val = 0;
|
||||
st25r3916_read_reg(handle, reg, ®_val);
|
||||
if((reg_val & ~clr_mask) != reg_val) {
|
||||
reg_val &= ~clr_mask;
|
||||
st25r3916_write_reg(handle, reg, reg_val);
|
||||
}
|
||||
}
|
||||
|
||||
void st25r3916_set_reg_bits(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t set_mask) {
|
||||
furi_assert(handle);
|
||||
|
||||
uint8_t reg_val = 0;
|
||||
st25r3916_read_reg(handle, reg, ®_val);
|
||||
if((reg_val | set_mask) != reg_val) {
|
||||
reg_val |= set_mask;
|
||||
st25r3916_write_reg(handle, reg, reg_val);
|
||||
}
|
||||
}
|
||||
|
||||
void st25r3916_change_reg_bits(
|
||||
FuriHalSpiBusHandle* handle,
|
||||
uint8_t reg,
|
||||
uint8_t mask,
|
||||
uint8_t value) {
|
||||
furi_assert(handle);
|
||||
|
||||
st25r3916_modify_reg(handle, reg, mask, (mask & value));
|
||||
}
|
||||
|
||||
void st25r3916_modify_reg(
|
||||
FuriHalSpiBusHandle* handle,
|
||||
uint8_t reg,
|
||||
uint8_t clr_mask,
|
||||
uint8_t set_mask) {
|
||||
furi_assert(handle);
|
||||
|
||||
uint8_t reg_val = 0;
|
||||
uint8_t new_val = 0;
|
||||
st25r3916_read_reg(handle, reg, ®_val);
|
||||
new_val = (reg_val & ~clr_mask) | set_mask;
|
||||
if(new_val != reg_val) {
|
||||
st25r3916_write_reg(handle, reg, new_val);
|
||||
}
|
||||
}
|
||||
|
||||
void st25r3916_change_test_reg_bits(
|
||||
FuriHalSpiBusHandle* handle,
|
||||
uint8_t reg,
|
||||
uint8_t mask,
|
||||
uint8_t value) {
|
||||
furi_assert(handle);
|
||||
|
||||
uint8_t reg_val = 0;
|
||||
uint8_t new_val = 0;
|
||||
st25r3916_read_test_reg(handle, reg, ®_val);
|
||||
new_val = (reg_val & ~mask) | (mask & value);
|
||||
if(new_val != reg_val) {
|
||||
st25r3916_write_test_reg(handle, reg, new_val);
|
||||
}
|
||||
}
|
||||
|
||||
bool st25r3916_check_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t mask, uint8_t val) {
|
||||
furi_assert(handle);
|
||||
|
||||
uint8_t reg_val = 0;
|
||||
st25r3916_read_reg(handle, reg, ®_val);
|
||||
return ((reg_val & mask) == val);
|
||||
}
|
||||
1144
lib/drivers/st25r3916_reg.h
Normal file
1144
lib/drivers/st25r3916_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user