mirror of
https://github.com/Next-Flip/Momentum-Firmware.git
synced 2026-04-24 03:29:57 -07:00
[FL-3867] Code formatting update (#3765)
* clang-format: AllowShortEnumsOnASingleLine: false * clang-format: InsertNewlineAtEOF: true * clang-format: Standard: c++20 * clang-format: AlignConsecutiveBitFields * clang-format: AlignConsecutiveMacros * clang-format: RemoveParentheses: ReturnStatement * clang-format: RemoveSemicolon: true * Restored RemoveParentheses: Leave, retained general changes for it * formatting: fixed logging TAGs * Formatting update for dev Co-authored-by: あく <alleteam@gmail.com>
This commit is contained in:
hedger
@@ -7,27 +7,27 @@
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#error Bit structures defined in this file is not portable to BE
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#endif
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#define BQ25896_ADDRESS 0xD6
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#define BQ25896_ADDRESS 0xD6
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#define BQ25896_I2C_TIMEOUT 50
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#define IILIM_1600 (1 << 5)
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#define IILIM_800 (1 << 4)
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#define IILIM_400 (1 << 3)
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#define IILIM_200 (1 << 2)
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#define IILIM_100 (1 << 1)
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#define IILIM_50 (1 << 0)
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#define IILIM_800 (1 << 4)
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#define IILIM_400 (1 << 3)
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#define IILIM_200 (1 << 2)
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#define IILIM_100 (1 << 1)
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#define IILIM_50 (1 << 0)
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typedef struct {
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uint8_t IINLIM : 6; // Input Current Limit, mA, offset: +100mA
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bool EN_ILIM : 1; // Enable ILIM Pin
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bool EN_HIZ : 1; // Enable HIZ Mode
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bool EN_ILIM : 1; // Enable ILIM Pin
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bool EN_HIZ : 1; // Enable HIZ Mode
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} REG00;
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#define VINDPM_OS_1600 (1 << 4)
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#define VINDPM_OS_800 (1 << 3)
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#define VINDPM_OS_400 (1 << 2)
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#define VINDPM_OS_200 (1 << 1)
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#define VINDPM_OS_100 (1 << 0)
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#define VINDPM_OS_800 (1 << 3)
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#define VINDPM_OS_400 (1 << 2)
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#define VINDPM_OS_200 (1 << 1)
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#define VINDPM_OS_100 (1 << 0)
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typedef enum {
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Bhot34 = 0b00, // – VBHOT1 Threshold (34.75%) (default)
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@@ -38,18 +38,18 @@ typedef enum {
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typedef struct {
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uint8_t VINDPM_OS : 5; // Input Voltage Limit Offset, mV
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bool BCOLD : 1; // Boost Mode Cold Temperature Monitor Threshold
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Bhot BHOT : 2; // Boost Mode Hot Temperature Monitor Threshold
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bool BCOLD : 1; // Boost Mode Cold Temperature Monitor Threshold
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Bhot BHOT : 2; // Boost Mode Hot Temperature Monitor Threshold
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} REG01;
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typedef struct {
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bool AUTO_DPDM_EN : 1; // Automatic Input Detection Enable
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bool FORCE_DPDM : 1; // Force Input Detection
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uint8_t RES : 2; // Reserved
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bool ICO_EN : 1; // Input Current Optimizer (ICO) Enable
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bool BOOST_FREQ : 1; // Boost Mode Frequency Selection
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bool CONV_RATE : 1; // ADC Conversion Rate Selection
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bool CONV_START : 1; // ADC Conversion Start Control
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bool FORCE_DPDM : 1; // Force Input Detection
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uint8_t RES : 2; // Reserved
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bool ICO_EN : 1; // Input Current Optimizer (ICO) Enable
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bool BOOST_FREQ : 1; // Boost Mode Frequency Selection
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bool CONV_RATE : 1; // ADC Conversion Rate Selection
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bool CONV_START : 1; // ADC Conversion Start Control
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} REG02;
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#define SYS_MIN_400 (1 << 2)
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@@ -58,45 +58,45 @@ typedef struct {
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typedef struct {
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bool MIN_VBAT_SEL : 1; // Minimum Battery Voltage (falling) to exit boost mode
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uint8_t SYS_MIN : 3; // Minimum System Voltage Limit, mV, offset: +3000mV
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bool CHG_CONFIG : 1; // Charge Enable Configuration
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bool OTG_CONFIG : 1; // Boost (OTG) Mode Configuration
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bool WD_RST : 1; // I2C Watchdog Timer Reset
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bool BAT_LOADEN : 1; // Battery Load (IBATLOAD) Enable
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uint8_t SYS_MIN : 3; // Minimum System Voltage Limit, mV, offset: +3000mV
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bool CHG_CONFIG : 1; // Charge Enable Configuration
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bool OTG_CONFIG : 1; // Boost (OTG) Mode Configuration
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bool WD_RST : 1; // I2C Watchdog Timer Reset
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bool BAT_LOADEN : 1; // Battery Load (IBATLOAD) Enable
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} REG03;
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#define ICHG_4096 (1 << 6)
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#define ICHG_2048 (1 << 5)
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#define ICHG_1024 (1 << 4)
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#define ICHG_512 (1 << 3)
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#define ICHG_256 (1 << 2)
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#define ICHG_128 (1 << 1)
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#define ICHG_64 (1 << 0)
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#define ICHG_512 (1 << 3)
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#define ICHG_256 (1 << 2)
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#define ICHG_128 (1 << 1)
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#define ICHG_64 (1 << 0)
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typedef struct {
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uint8_t ICHG : 7; // Fast Charge Current Limit, mA
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uint8_t ICHG : 7; // Fast Charge Current Limit, mA
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bool EN_PUMPX : 1; // Current pulse control Enable
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} REG04;
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#define IPRETERM_512 (1 << 3)
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#define IPRETERM_256 (1 << 2)
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#define IPRETERM_128 (1 << 1)
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#define IPRETERM_64 (1 << 0)
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#define IPRETERM_64 (1 << 0)
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typedef struct {
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uint8_t ITERM : 4; // Termination Current Limit, offset: +64mA
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uint8_t ITERM : 4; // Termination Current Limit, offset: +64mA
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uint8_t IPRECHG : 4; // Precharge Current Limit, offset: +64mA
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} REG05;
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#define VREG_512 (1 << 5)
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#define VREG_256 (1 << 4)
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#define VREG_128 (1 << 3)
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#define VREG_64 (1 << 2)
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#define VREG_32 (1 << 1)
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#define VREG_16 (1 << 0)
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#define VREG_64 (1 << 2)
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#define VREG_32 (1 << 1)
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#define VREG_16 (1 << 0)
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typedef struct {
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bool VRECHG : 1; // Battery Recharge Threshold Offset
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bool VRECHG : 1; // Battery Recharge Threshold Offset
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bool BATLOWV : 1; // Battery Precharge to Fast Charge Threshold
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uint8_t VREG : 6; // Charge Voltage Limit, offset: +3840mV
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} REG06;
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@@ -116,12 +116,12 @@ typedef enum {
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} ChgTimer;
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typedef struct {
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bool JEITA_ISET : 1; // JEITA Low Temperature Current Setting
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bool JEITA_ISET : 1; // JEITA Low Temperature Current Setting
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ChgTimer CHG_TIMER : 2; // Fast Charge Timer Setting
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bool EN_TIMER : 1; // Charging Safety Timer Enable
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Watchdog WATCHDOG : 2; // I2C Watchdog Timer Setting
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bool STAT_DIS : 1; // STAT Pin Disable
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bool EN_TERM : 1; // Charging Termination Enable
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bool EN_TIMER : 1; // Charging Safety Timer Enable
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Watchdog WATCHDOG : 2; // I2C Watchdog Timer Setting
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bool STAT_DIS : 1; // STAT Pin Disable
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bool EN_TERM : 1; // Charging Termination Enable
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} REG07;
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#define BAT_COMP_80 (1 << 2)
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@@ -129,35 +129,35 @@ typedef struct {
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#define BAT_COMP_20 (1 << 0)
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#define VCLAMP_128 (1 << 2)
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#define VCLAMP_64 (1 << 1)
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#define VCLAMP_32 (1 << 0)
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#define VCLAMP_64 (1 << 1)
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#define VCLAMP_32 (1 << 0)
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#define TREG_60 (0b00)
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#define TREG_80 (0b01)
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#define TREG_60 (0b00)
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#define TREG_80 (0b01)
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#define TREG_100 (0b10)
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#define TREG_120 (0b11)
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typedef struct {
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uint8_t TREG : 2; // Thermal Regulation Threshold
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uint8_t VCLAMP : 3; // IR Compensation Voltage Clamp
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uint8_t TREG : 2; // Thermal Regulation Threshold
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uint8_t VCLAMP : 3; // IR Compensation Voltage Clamp
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uint8_t BAT_COMP : 3; // IR Compensation Resistor Setting
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} REG08;
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typedef struct {
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bool PUMPX_DN : 1; // Current pulse control voltage down enable
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bool PUMPX_UP : 1; // Current pulse control voltage up enable
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bool PUMPX_DN : 1; // Current pulse control voltage down enable
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bool PUMPX_UP : 1; // Current pulse control voltage up enable
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bool BATFET_RST_EN : 1; // BATFET full system reset enable
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bool BATFET_DLY : 1; // BATFET turn off delay control
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bool JEITA_VSET : 1; // JEITA High Temperature Voltage Setting
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bool BATFET_DIS : 1; // Force BATFET off to enable ship mode
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bool TMR2X_EN : 1; // Safety Timer Setting during DPM or Thermal Regulation
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bool FORCE_ICO : 1; // Force Start Input Current Optimizer
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bool BATFET_DLY : 1; // BATFET turn off delay control
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bool JEITA_VSET : 1; // JEITA High Temperature Voltage Setting
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bool BATFET_DIS : 1; // Force BATFET off to enable ship mode
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bool TMR2X_EN : 1; // Safety Timer Setting during DPM or Thermal Regulation
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bool FORCE_ICO : 1; // Force Start Input Current Optimizer
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} REG09;
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#define BOOSTV_512 (1 << 3)
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#define BOOSTV_256 (1 << 2)
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#define BOOSTV_128 (1 << 1)
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#define BOOSTV_64 (1 << 0)
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#define BOOSTV_64 (1 << 0)
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typedef enum {
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BoostLim_500 = 0b000,
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@@ -172,8 +172,8 @@ typedef enum {
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typedef struct {
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uint8_t BOOST_LIM : 3; // Boost Mode Current Limit
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bool PFM_OTG_DIS : 1; // PFM mode allowed in boost mode
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uint8_t BOOSTV : 4; // Boost Mode Voltage Regulation, offset: +4550mV
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bool PFM_OTG_DIS : 1; // PFM mode allowed in boost mode
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uint8_t BOOSTV : 4; // Boost Mode Voltage Regulation, offset: +4550mV
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} REG0A;
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typedef enum {
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@@ -191,9 +191,9 @@ typedef enum {
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} ChrgStat;
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typedef struct {
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bool VSYS_STAT : 1; // VSYS Regulation Status
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bool RES : 1; // Reserved: Always reads 1
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bool PG_STAT : 1; // Power Good Status
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bool VSYS_STAT : 1; // VSYS Regulation Status
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bool RES : 1; // Reserved: Always reads 1
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bool PG_STAT : 1; // Power Good Status
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ChrgStat CHRG_STAT : 2; // Charging Status
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VBusStat VBUS_STAT : 3; // VBUS Status register
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} REG0B;
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@@ -214,49 +214,49 @@ typedef enum {
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} NtcFault;
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typedef struct {
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NtcFault NTC_FAULT : 3; // NTC Fault Status
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bool BAT_FAULT : 1; // Battery Fault Status
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NtcFault NTC_FAULT : 3; // NTC Fault Status
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bool BAT_FAULT : 1; // Battery Fault Status
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ChrgFault CHRG_FAULT : 2; // Charge Fault Status
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bool BOOST_FAULT : 1; // Boost Mode Fault Status
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bool WATCHDOG_FAULT : 1; // Watchdog Fault Status
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bool BOOST_FAULT : 1; // Boost Mode Fault Status
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bool WATCHDOG_FAULT : 1; // Watchdog Fault Status
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} REG0C;
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#define VINDPM_6400 (1 << 6)
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#define VINDPM_3200 (1 << 5)
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#define VINDPM_1600 (1 << 4)
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#define VINDPM_800 (1 << 3)
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#define VINDPM_400 (1 << 2)
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#define VINDPM_200 (1 << 1)
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#define VINDPM_100 (1 << 0)
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#define VINDPM_800 (1 << 3)
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#define VINDPM_400 (1 << 2)
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#define VINDPM_200 (1 << 1)
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#define VINDPM_100 (1 << 0)
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typedef struct {
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uint8_t VINDPM : 7; // Absolute VINDPM Threshold, offset: +2600mV
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uint8_t VINDPM : 7; // Absolute VINDPM Threshold, offset: +2600mV
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bool FORCE_VINDPM : 1; // VINDPM Threshold Setting Method
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} REG0D;
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typedef struct {
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uint8_t BATV : 7; // ADC conversion of Battery Voltage (VBAT), offset: +2304mV
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uint8_t BATV : 7; // ADC conversion of Battery Voltage (VBAT), offset: +2304mV
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bool THERM_STAT : 1; // Thermal Regulation Status
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} REG0E;
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typedef struct {
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uint8_t SYSV : 7; // ADDC conversion of System Voltage (VSYS), offset: +2304mV
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uint8_t RES : 1; // Reserved: Always reads 0
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uint8_t RES : 1; // Reserved: Always reads 0
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} REG0F;
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typedef struct {
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uint8_t TSPCT : 7; // ADC conversion of TS Voltage (TS) as percentage of REGN, offset: +21%
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uint8_t RES : 1; // Reserved: Always reads 0
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uint8_t RES : 1; // Reserved: Always reads 0
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} REG10;
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typedef struct {
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uint8_t VBUSV : 7; // ADC conversion of VBUS voltage (VBUS), offset: +2600mV
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bool VBUS_GD : 1; // VBUS Good Status
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bool VBUS_GD : 1; // VBUS Good Status
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} REG11;
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typedef struct {
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uint8_t ICHGR : 7; // ADC conversion of Charge Current (IBAT) when VBAT > VBATSHORT
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uint8_t RES : 1; // Reserved: Always reads 0
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uint8_t RES : 1; // Reserved: Always reads 0
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} REG12;
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typedef struct {
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@@ -267,9 +267,9 @@ typedef struct {
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} REG13;
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typedef struct {
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uint8_t DEV_REV : 2; // Device Revision
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bool TS_PROFILE : 1; // Temperature Profile
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uint8_t PN : 3; // Device Configuration
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uint8_t DEV_REV : 2; // Device Revision
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bool TS_PROFILE : 1; // Temperature Profile
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uint8_t PN : 3; // Device Configuration
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bool ICO_OPTIMIZED : 1; // Input Current Optimizer (ICO) Status
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bool REG_RST : 1; // Register Reset
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bool REG_RST : 1; // Register Reset
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} REG14;
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@@ -4,45 +4,45 @@
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#include <stdbool.h>
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#include <furi_hal_i2c.h>
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#define BQ27220_ERROR 0x0
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#define BQ27220_ERROR 0x0
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#define BQ27220_SUCCESS 0x1
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typedef struct {
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// Low byte, Low bit first
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bool DSG : 1; // The device is in DISCHARGE
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bool SYSDWN : 1; // System down bit indicating the system should shut down
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bool TDA : 1; // Terminate Discharge Alarm
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bool DSG : 1; // The device is in DISCHARGE
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bool SYSDWN : 1; // System down bit indicating the system should shut down
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bool TDA : 1; // Terminate Discharge Alarm
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bool BATTPRES : 1; // Battery Present detected
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bool AUTH_GD : 1; // Detect inserted battery
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bool OCVGD : 1; // Good OCV measurement taken
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bool TCA : 1; // Terminate Charge Alarm
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bool RSVD : 1; // Reserved
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bool AUTH_GD : 1; // Detect inserted battery
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bool OCVGD : 1; // Good OCV measurement taken
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bool TCA : 1; // Terminate Charge Alarm
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bool RSVD : 1; // Reserved
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// High byte, Low bit first
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bool CHGINH : 1; // Charge inhibit
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bool FC : 1; // Full-charged is detected
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bool OTD : 1; // Overtemperature in discharge condition is detected
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bool OTC : 1; // Overtemperature in charge condition is detected
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bool SLEEP : 1; // Device is operating in SLEEP mode when set
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bool OCVFAIL : 1; // Status bit indicating that the OCV reading failed due to current
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bool OCVCOMP : 1; // An OCV measurement update is complete
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bool FD : 1; // Full-discharge is detected
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bool CHGINH : 1; // Charge inhibit
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bool FC : 1; // Full-charged is detected
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bool OTD : 1; // Overtemperature in discharge condition is detected
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bool OTC : 1; // Overtemperature in charge condition is detected
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bool SLEEP : 1; // Device is operating in SLEEP mode when set
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bool OCVFAIL : 1; // Status bit indicating that the OCV reading failed due to current
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bool OCVCOMP : 1; // An OCV measurement update is complete
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bool FD : 1; // Full-discharge is detected
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} BatteryStatus;
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_Static_assert(sizeof(BatteryStatus) == 2, "Incorrect structure size");
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typedef struct {
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// Low byte, Low bit first
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bool CALMD : 1; /**< Calibration mode enabled */
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bool CALMD : 1; /**< Calibration mode enabled */
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uint8_t SEC : 2; /**< Current security access */
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bool EDV2 : 1; /**< EDV2 threshold exceeded */
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bool EDV2 : 1; /**< EDV2 threshold exceeded */
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bool VDQ : 1; /**< Indicates if Current discharge cycle is NOT qualified or qualified for an FCC updated */
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bool INITCOMP : 1; /**< gauge initialization is complete */
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bool SMTH : 1; /**< RemainingCapacity is scaled by smooth engine */
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bool BTPINT : 1; /**< BTP threshold has been crossed */
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bool INITCOMP : 1; /**< gauge initialization is complete */
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bool SMTH : 1; /**< RemainingCapacity is scaled by smooth engine */
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bool BTPINT : 1; /**< BTP threshold has been crossed */
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// High byte, Low bit first
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uint8_t RSVD1 : 2;
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uint8_t RSVD1 : 2;
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bool CFGUPDATE : 1; /**< Gauge is in CONFIG UPDATE mode */
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uint8_t RSVD0 : 5;
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uint8_t RSVD0 : 5;
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} OperationStatus;
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_Static_assert(sizeof(OperationStatus) == 2, "Incorrect structure size");
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@@ -67,18 +67,18 @@ struct BQ27220DMData {
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typedef struct {
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// Low byte, Low bit first
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const bool CCT : 1;
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const bool CSYNC : 1;
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const bool RSVD0 : 1;
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const bool EDV_CMP : 1;
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const bool SC : 1;
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const bool CCT : 1;
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const bool CSYNC : 1;
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const bool RSVD0 : 1;
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const bool EDV_CMP : 1;
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const bool SC : 1;
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const bool FIXED_EDV0 : 1;
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const uint8_t RSVD1 : 2;
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const uint8_t RSVD1 : 2;
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// High byte, Low bit first
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const bool FCC_LIM : 1;
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const bool RSVD2 : 1;
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const bool FCC_LIM : 1;
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const bool RSVD2 : 1;
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const bool FC_FOR_VDQ : 1;
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const bool IGNORE_SD : 1;
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const bool SME0 : 1;
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const uint8_t RSVD3 : 3;
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const bool IGNORE_SD : 1;
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const bool SME0 : 1;
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const uint8_t RSVD3 : 3;
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} BQ27220DMGaugingConfig;
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@@ -1,68 +1,68 @@
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#pragma once
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#define BQ27220_ADDRESS 0xAA
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#define BQ27220_ADDRESS 0xAA
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#define BQ27220_I2C_TIMEOUT 50
|
||||
|
||||
#define CommandControl 0x00
|
||||
#define CommandAtRate 0x02
|
||||
#define CommandAtRateTimeToEmpty 0x04
|
||||
#define CommandTemperature 0x06
|
||||
#define CommandVoltage 0x08
|
||||
#define CommandBatteryStatus 0x0A
|
||||
#define CommandCurrent 0x0C
|
||||
#define CommandRemainingCapacity 0x10
|
||||
#define CommandFullChargeCapacity 0x12
|
||||
#define CommandAverageCurrent 0x14
|
||||
#define CommandTimeToEmpty 0x16
|
||||
#define CommandTimeToFull 0x18
|
||||
#define CommandStandbyCurrent 0x1A
|
||||
#define CommandStandbyTimeToEmpty 0x1C
|
||||
#define CommandMaxLoadCurrent 0x1E
|
||||
#define CommandMaxLoadTimeToEmpty 0x20
|
||||
#define CommandRawCoulombCount 0x22
|
||||
#define CommandAveragePower 0x24
|
||||
#define CommandControl 0x00
|
||||
#define CommandAtRate 0x02
|
||||
#define CommandAtRateTimeToEmpty 0x04
|
||||
#define CommandTemperature 0x06
|
||||
#define CommandVoltage 0x08
|
||||
#define CommandBatteryStatus 0x0A
|
||||
#define CommandCurrent 0x0C
|
||||
#define CommandRemainingCapacity 0x10
|
||||
#define CommandFullChargeCapacity 0x12
|
||||
#define CommandAverageCurrent 0x14
|
||||
#define CommandTimeToEmpty 0x16
|
||||
#define CommandTimeToFull 0x18
|
||||
#define CommandStandbyCurrent 0x1A
|
||||
#define CommandStandbyTimeToEmpty 0x1C
|
||||
#define CommandMaxLoadCurrent 0x1E
|
||||
#define CommandMaxLoadTimeToEmpty 0x20
|
||||
#define CommandRawCoulombCount 0x22
|
||||
#define CommandAveragePower 0x24
|
||||
#define CommandInternalTemperature 0x28
|
||||
#define CommandCycleCount 0x2A
|
||||
#define CommandStateOfCharge 0x2C
|
||||
#define CommandStateOfHealth 0x2E
|
||||
#define CommandChargeVoltage 0x30
|
||||
#define CommandChargeCurrent 0x32
|
||||
#define CommandBTPDischargeSet 0x34
|
||||
#define CommandBTPChargeSet 0x36
|
||||
#define CommandOperationStatus 0x3A
|
||||
#define CommandDesignCapacity 0x3C
|
||||
#define CommandSelectSubclass 0x3E
|
||||
#define CommandMACData 0x40
|
||||
#define CommandMACDataSum 0x60
|
||||
#define CommandMACDataLen 0x61
|
||||
#define CommandAnalogCount 0x79
|
||||
#define CommandRawCurrent 0x7A
|
||||
#define CommandRawVoltage 0x7C
|
||||
#define CommandRawIntTemp 0x7E
|
||||
#define CommandCycleCount 0x2A
|
||||
#define CommandStateOfCharge 0x2C
|
||||
#define CommandStateOfHealth 0x2E
|
||||
#define CommandChargeVoltage 0x30
|
||||
#define CommandChargeCurrent 0x32
|
||||
#define CommandBTPDischargeSet 0x34
|
||||
#define CommandBTPChargeSet 0x36
|
||||
#define CommandOperationStatus 0x3A
|
||||
#define CommandDesignCapacity 0x3C
|
||||
#define CommandSelectSubclass 0x3E
|
||||
#define CommandMACData 0x40
|
||||
#define CommandMACDataSum 0x60
|
||||
#define CommandMACDataLen 0x61
|
||||
#define CommandAnalogCount 0x79
|
||||
#define CommandRawCurrent 0x7A
|
||||
#define CommandRawVoltage 0x7C
|
||||
#define CommandRawIntTemp 0x7E
|
||||
|
||||
#define Control_CONTROL_STATUS 0x0000
|
||||
#define Control_DEVICE_NUMBER 0x0001
|
||||
#define Control_FW_VERSION 0x0002
|
||||
#define Control_BOARD_OFFSET 0x0009
|
||||
#define Control_CC_OFFSET 0x000A
|
||||
#define Control_CC_OFFSET_SAVE 0x000B
|
||||
#define Control_OCV_CMD 0x000C
|
||||
#define Control_BAT_INSERT 0x000D
|
||||
#define Control_BAT_REMOVE 0x000E
|
||||
#define Control_SET_SNOOZE 0x0013
|
||||
#define Control_CLEAR_SNOOZE 0x0014
|
||||
#define Control_SET_PROFILE_1 0x0015
|
||||
#define Control_SET_PROFILE_2 0x0016
|
||||
#define Control_SET_PROFILE_3 0x0017
|
||||
#define Control_SET_PROFILE_4 0x0018
|
||||
#define Control_SET_PROFILE_5 0x0019
|
||||
#define Control_SET_PROFILE_6 0x001A
|
||||
#define Control_CAL_TOGGLE 0x002D
|
||||
#define Control_SEALED 0x0030
|
||||
#define Control_RESET 0x0041
|
||||
#define Control_EXIT_CAL 0x0080
|
||||
#define Control_ENTER_CAL 0x0081
|
||||
#define Control_ENTER_CFG_UPDATE 0x0090
|
||||
#define Control_CONTROL_STATUS 0x0000
|
||||
#define Control_DEVICE_NUMBER 0x0001
|
||||
#define Control_FW_VERSION 0x0002
|
||||
#define Control_BOARD_OFFSET 0x0009
|
||||
#define Control_CC_OFFSET 0x000A
|
||||
#define Control_CC_OFFSET_SAVE 0x000B
|
||||
#define Control_OCV_CMD 0x000C
|
||||
#define Control_BAT_INSERT 0x000D
|
||||
#define Control_BAT_REMOVE 0x000E
|
||||
#define Control_SET_SNOOZE 0x0013
|
||||
#define Control_CLEAR_SNOOZE 0x0014
|
||||
#define Control_SET_PROFILE_1 0x0015
|
||||
#define Control_SET_PROFILE_2 0x0016
|
||||
#define Control_SET_PROFILE_3 0x0017
|
||||
#define Control_SET_PROFILE_4 0x0018
|
||||
#define Control_SET_PROFILE_5 0x0019
|
||||
#define Control_SET_PROFILE_6 0x001A
|
||||
#define Control_CAL_TOGGLE 0x002D
|
||||
#define Control_SEALED 0x0030
|
||||
#define Control_RESET 0x0041
|
||||
#define Control_EXIT_CAL 0x0080
|
||||
#define Control_ENTER_CAL 0x0081
|
||||
#define Control_ENTER_CFG_UPDATE 0x0090
|
||||
#define Control_EXIT_CFG_UPDATE_REINIT 0x0091
|
||||
#define Control_EXIT_CFG_UPDATE 0x0092
|
||||
#define Control_RETURN_TO_ROM 0x0F00
|
||||
#define Control_EXIT_CFG_UPDATE 0x0092
|
||||
#define Control_RETURN_TO_ROM 0x0F00
|
||||
|
||||
@@ -185,4 +185,4 @@ uint8_t cc1101_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* data, uint8_t* si
|
||||
furi_hal_spi_bus_trx(handle, NULL, data, *size, CC1101_TIMEOUT);
|
||||
|
||||
return *size;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -9,65 +9,65 @@ extern "C" {
|
||||
|
||||
/* Frequency Synthesizer constants */
|
||||
#define CC1101_QUARTZ 26000000
|
||||
#define CC1101_FMASK 0xFFFFFF
|
||||
#define CC1101_FDIV 0x10000
|
||||
#define CC1101_IFDIV 0x400
|
||||
#define CC1101_FMASK 0xFFFFFF
|
||||
#define CC1101_FDIV 0x10000
|
||||
#define CC1101_IFDIV 0x400
|
||||
|
||||
/* IO Bus constants */
|
||||
#define CC1101_TIMEOUT 250
|
||||
|
||||
/* Bits and pieces */
|
||||
#define CC1101_READ (1 << 7) /** Read Bit */
|
||||
#define CC1101_READ (1 << 7) /** Read Bit */
|
||||
#define CC1101_BURST (1 << 6) /** Burst Bit */
|
||||
|
||||
/* Common registers, CC1101_BURST and CC1101_WRITE behaves as expected */
|
||||
#define CC1101_IOCFG2 0x00 /** GDO2 output pin configuration */
|
||||
#define CC1101_IOCFG1 0x01 /** GDO1 output pin configuration */
|
||||
#define CC1101_IOCFG0 0x02 /** GDO0 output pin configuration */
|
||||
#define CC1101_FIFOTHR 0x03 /** RX FIFO and TX FIFO thresholds */
|
||||
#define CC1101_SYNC1 0x04 /** Sync word, high byte */
|
||||
#define CC1101_SYNC0 0x05 /** Sync word, low byte */
|
||||
#define CC1101_PKTLEN 0x06 /** Packet length */
|
||||
#define CC1101_IOCFG2 0x00 /** GDO2 output pin configuration */
|
||||
#define CC1101_IOCFG1 0x01 /** GDO1 output pin configuration */
|
||||
#define CC1101_IOCFG0 0x02 /** GDO0 output pin configuration */
|
||||
#define CC1101_FIFOTHR 0x03 /** RX FIFO and TX FIFO thresholds */
|
||||
#define CC1101_SYNC1 0x04 /** Sync word, high byte */
|
||||
#define CC1101_SYNC0 0x05 /** Sync word, low byte */
|
||||
#define CC1101_PKTLEN 0x06 /** Packet length */
|
||||
#define CC1101_PKTCTRL1 0x07 /** Packet automation control */
|
||||
#define CC1101_PKTCTRL0 0x08 /** Packet automation control */
|
||||
#define CC1101_ADDR 0x09 /** Device address */
|
||||
#define CC1101_CHANNR 0x0A /** Channel number */
|
||||
#define CC1101_FSCTRL1 0x0B /** Frequency synthesizer control */
|
||||
#define CC1101_FSCTRL0 0x0C /** Frequency synthesizer control */
|
||||
#define CC1101_FREQ2 0x0D /** Frequency control word, high byte */
|
||||
#define CC1101_FREQ1 0x0E /** Frequency control word, middle byte */
|
||||
#define CC1101_FREQ0 0x0F /** Frequency control word, low byte */
|
||||
#define CC1101_MDMCFG4 0x10 /** Modem configuration */
|
||||
#define CC1101_MDMCFG3 0x11 /** Modem configuration */
|
||||
#define CC1101_MDMCFG2 0x12 /** Modem configuration */
|
||||
#define CC1101_MDMCFG1 0x13 /** Modem configuration */
|
||||
#define CC1101_MDMCFG0 0x14 /** Modem configuration */
|
||||
#define CC1101_DEVIATN 0x15 /** Modem deviation setting */
|
||||
#define CC1101_MCSM2 0x16 /** Main Radio Control State Machine configuration */
|
||||
#define CC1101_MCSM1 0x17 /** Main Radio Control State Machine configuration */
|
||||
#define CC1101_MCSM0 0x18 /** Main Radio Control State Machine configuration */
|
||||
#define CC1101_FOCCFG 0x19 /** Frequency Offset Compensation configuration */
|
||||
#define CC1101_BSCFG 0x1A /** Bit Synchronization configuration */
|
||||
#define CC1101_ADDR 0x09 /** Device address */
|
||||
#define CC1101_CHANNR 0x0A /** Channel number */
|
||||
#define CC1101_FSCTRL1 0x0B /** Frequency synthesizer control */
|
||||
#define CC1101_FSCTRL0 0x0C /** Frequency synthesizer control */
|
||||
#define CC1101_FREQ2 0x0D /** Frequency control word, high byte */
|
||||
#define CC1101_FREQ1 0x0E /** Frequency control word, middle byte */
|
||||
#define CC1101_FREQ0 0x0F /** Frequency control word, low byte */
|
||||
#define CC1101_MDMCFG4 0x10 /** Modem configuration */
|
||||
#define CC1101_MDMCFG3 0x11 /** Modem configuration */
|
||||
#define CC1101_MDMCFG2 0x12 /** Modem configuration */
|
||||
#define CC1101_MDMCFG1 0x13 /** Modem configuration */
|
||||
#define CC1101_MDMCFG0 0x14 /** Modem configuration */
|
||||
#define CC1101_DEVIATN 0x15 /** Modem deviation setting */
|
||||
#define CC1101_MCSM2 0x16 /** Main Radio Control State Machine configuration */
|
||||
#define CC1101_MCSM1 0x17 /** Main Radio Control State Machine configuration */
|
||||
#define CC1101_MCSM0 0x18 /** Main Radio Control State Machine configuration */
|
||||
#define CC1101_FOCCFG 0x19 /** Frequency Offset Compensation configuration */
|
||||
#define CC1101_BSCFG 0x1A /** Bit Synchronization configuration */
|
||||
#define CC1101_AGCCTRL2 0x1B /** AGC control */
|
||||
#define CC1101_AGCCTRL1 0x1C /** AGC control */
|
||||
#define CC1101_AGCCTRL0 0x1D /** AGC control */
|
||||
#define CC1101_WOREVT1 0x1E /** High byte Event 0 timeout */
|
||||
#define CC1101_WOREVT0 0x1F /** Low byte Event 0 timeout */
|
||||
#define CC1101_WORCTRL 0x20 /** Wake On Radio control */
|
||||
#define CC1101_FREND1 0x21 /** Front end RX configuration */
|
||||
#define CC1101_FREND0 0x22 /** Front end TX configuration */
|
||||
#define CC1101_FSCAL3 0x23 /** Frequency synthesizer calibration */
|
||||
#define CC1101_FSCAL2 0x24 /** Frequency synthesizer calibration */
|
||||
#define CC1101_FSCAL1 0x25 /** Frequency synthesizer calibration */
|
||||
#define CC1101_FSCAL0 0x26 /** Frequency synthesizer calibration */
|
||||
#define CC1101_RCCTRL1 0x27 /** RC oscillator configuration */
|
||||
#define CC1101_RCCTRL0 0x28 /** RC oscillator configuration */
|
||||
#define CC1101_FSTEST 0x29 /** Frequency synthesizer calibration control */
|
||||
#define CC1101_PTEST 0x2A /** Production test */
|
||||
#define CC1101_AGCTEST 0x2B /** AGC test */
|
||||
#define CC1101_TEST2 0x2C /** Various test settings */
|
||||
#define CC1101_TEST1 0x2D /** Various test settings */
|
||||
#define CC1101_TEST0 0x2E /** Various test settings */
|
||||
#define CC1101_WOREVT1 0x1E /** High byte Event 0 timeout */
|
||||
#define CC1101_WOREVT0 0x1F /** Low byte Event 0 timeout */
|
||||
#define CC1101_WORCTRL 0x20 /** Wake On Radio control */
|
||||
#define CC1101_FREND1 0x21 /** Front end RX configuration */
|
||||
#define CC1101_FREND0 0x22 /** Front end TX configuration */
|
||||
#define CC1101_FSCAL3 0x23 /** Frequency synthesizer calibration */
|
||||
#define CC1101_FSCAL2 0x24 /** Frequency synthesizer calibration */
|
||||
#define CC1101_FSCAL1 0x25 /** Frequency synthesizer calibration */
|
||||
#define CC1101_FSCAL0 0x26 /** Frequency synthesizer calibration */
|
||||
#define CC1101_RCCTRL1 0x27 /** RC oscillator configuration */
|
||||
#define CC1101_RCCTRL0 0x28 /** RC oscillator configuration */
|
||||
#define CC1101_FSTEST 0x29 /** Frequency synthesizer calibration control */
|
||||
#define CC1101_PTEST 0x2A /** Production test */
|
||||
#define CC1101_AGCTEST 0x2B /** AGC test */
|
||||
#define CC1101_TEST2 0x2C /** Various test settings */
|
||||
#define CC1101_TEST1 0x2D /** Various test settings */
|
||||
#define CC1101_TEST0 0x2E /** Various test settings */
|
||||
|
||||
/* Strobe registers, CC1101_BURST is not available, CC1101_WRITE ignored */
|
||||
#define CC1101_STROBE_SRES 0x30 /** Reset chip. */
|
||||
@@ -95,15 +95,15 @@ extern "C" {
|
||||
0x3D /** No operation. May be used to get access to the chip status byte.*/
|
||||
|
||||
/* Status registers, must be accessed with CC1101_BURST, but one by one */
|
||||
#define CC1101_STATUS_PARTNUM 0x30 /** Chip ID Part Number */
|
||||
#define CC1101_STATUS_VERSION 0x31 /** Chip ID Version */
|
||||
#define CC1101_STATUS_FREQEST 0x32 /** Frequency Offset Estimate from Demodulator */
|
||||
#define CC1101_STATUS_LQI 0x33 /** Demodulator Estimate for Link Quality, 7bit-CRC, 6..0-LQI*/
|
||||
#define CC1101_STATUS_RSSI 0x34 /** Received Signal Strength Indication */
|
||||
#define CC1101_STATUS_MARCSTATE 0x35 /** Main Radio Control State Machine State */
|
||||
#define CC1101_STATUS_WORTIME1 0x36 /** High Byte of WOR Time */
|
||||
#define CC1101_STATUS_WORTIME0 0x37 /** Low Byte of WOR Time */
|
||||
#define CC1101_STATUS_PKTSTATUS 0x38 /** Current GDOx Status and Packet Status */
|
||||
#define CC1101_STATUS_PARTNUM 0x30 /** Chip ID Part Number */
|
||||
#define CC1101_STATUS_VERSION 0x31 /** Chip ID Version */
|
||||
#define CC1101_STATUS_FREQEST 0x32 /** Frequency Offset Estimate from Demodulator */
|
||||
#define CC1101_STATUS_LQI 0x33 /** Demodulator Estimate for Link Quality, 7bit-CRC, 6..0-LQI*/
|
||||
#define CC1101_STATUS_RSSI 0x34 /** Received Signal Strength Indication */
|
||||
#define CC1101_STATUS_MARCSTATE 0x35 /** Main Radio Control State Machine State */
|
||||
#define CC1101_STATUS_WORTIME1 0x36 /** High Byte of WOR Time */
|
||||
#define CC1101_STATUS_WORTIME0 0x37 /** Low Byte of WOR Time */
|
||||
#define CC1101_STATUS_PKTSTATUS 0x38 /** Current GDOx Status and Packet Status */
|
||||
#define CC1101_STATUS_VCO_VC_DAC 0x39 /** Current Setting from PLL Calibration Module */
|
||||
#define CC1101_STATUS_TXBYTES \
|
||||
0x3A /** Underflow and Number of Bytes, 7bit-Underflow, 6..0-Number of Bytes*/
|
||||
@@ -188,8 +188,8 @@ typedef enum {
|
||||
|
||||
typedef struct {
|
||||
uint8_t FIFO_BYTES_AVAILABLE : 4;
|
||||
CC1101State STATE : 3;
|
||||
bool CHIP_RDYn : 1;
|
||||
CC1101State STATE : 3;
|
||||
bool CHIP_RDYn : 1;
|
||||
} CC1101Status;
|
||||
|
||||
typedef union {
|
||||
@@ -198,12 +198,12 @@ typedef union {
|
||||
} CC1101StatusRaw;
|
||||
|
||||
typedef struct {
|
||||
uint8_t NUM_TXBYTES : 7;
|
||||
uint8_t NUM_TXBYTES : 7;
|
||||
bool TXFIFO_UNDERFLOW : 1;
|
||||
} CC1101TxBytes;
|
||||
|
||||
typedef struct {
|
||||
uint8_t NUM_RXBYTES : 7;
|
||||
uint8_t NUM_RXBYTES : 7;
|
||||
bool RXFIFO_OVERFLOW : 1;
|
||||
} CC1101RxBytes;
|
||||
|
||||
|
||||
@@ -4,17 +4,17 @@
|
||||
#error Bit structures defined in this file is not portable to BE
|
||||
#endif
|
||||
|
||||
#define LP5562_ADDRESS 0x60
|
||||
#define LP5562_ADDRESS 0x60
|
||||
#define LP5562_I2C_TIMEOUT 50
|
||||
|
||||
#define LP5562_CHANNEL_RED_CURRENT_REGISTER 0x07
|
||||
#define LP5562_CHANNEL_RED_CURRENT_REGISTER 0x07
|
||||
#define LP5562_CHANNEL_GREEN_CURRENT_REGISTER 0x06
|
||||
#define LP5562_CHANNEL_BLUE_CURRENT_REGISTER 0x05
|
||||
#define LP5562_CHANNEL_BLUE_CURRENT_REGISTER 0x05
|
||||
#define LP5562_CHANNEL_WHITE_CURRENT_REGISTER 0x0F
|
||||
|
||||
#define LP5562_CHANNEL_RED_VALUE_REGISTER 0x04
|
||||
#define LP5562_CHANNEL_RED_VALUE_REGISTER 0x04
|
||||
#define LP5562_CHANNEL_GREEN_VALUE_REGISTER 0x03
|
||||
#define LP5562_CHANNEL_BLUE_VALUE_REGISTER 0x02
|
||||
#define LP5562_CHANNEL_BLUE_VALUE_REGISTER 0x02
|
||||
#define LP5562_CHANNEL_WHITE_VALUE_REGISTER 0x0E
|
||||
|
||||
typedef enum {
|
||||
@@ -28,8 +28,8 @@ typedef struct {
|
||||
EngExec ENG3_EXEC : 2;
|
||||
EngExec ENG2_EXEC : 2;
|
||||
EngExec ENG1_EXEC : 2;
|
||||
bool CHIP_EN : 1;
|
||||
bool LOG_EN : 1;
|
||||
bool CHIP_EN : 1;
|
||||
bool LOG_EN : 1;
|
||||
} Reg00_Enable;
|
||||
|
||||
typedef enum {
|
||||
@@ -43,39 +43,39 @@ typedef struct {
|
||||
EngMode ENG3_MODE : 2;
|
||||
EngMode ENG2_MODE : 2;
|
||||
EngMode ENG1_MODE : 2;
|
||||
uint8_t reserved : 2;
|
||||
uint8_t reserved : 2;
|
||||
} Reg01_OpMode;
|
||||
|
||||
typedef struct {
|
||||
bool INT_CLK_EN : 1;
|
||||
bool CLK_DET_EN : 1;
|
||||
bool INT_CLK_EN : 1;
|
||||
bool CLK_DET_EN : 1;
|
||||
uint8_t reserved0 : 3;
|
||||
bool PS_EN : 1;
|
||||
bool PWM_HF : 1;
|
||||
bool PS_EN : 1;
|
||||
bool PWM_HF : 1;
|
||||
uint8_t reserved1 : 1;
|
||||
} Reg08_Config;
|
||||
|
||||
typedef struct {
|
||||
uint8_t pc : 3;
|
||||
uint8_t pc : 3;
|
||||
uint8_t reserved : 5;
|
||||
} Reg09_Engine1PC;
|
||||
|
||||
typedef struct {
|
||||
uint8_t pc : 3;
|
||||
uint8_t pc : 3;
|
||||
uint8_t reserved : 5;
|
||||
} Reg0A_Engine2PC;
|
||||
|
||||
typedef struct {
|
||||
uint8_t pc : 3;
|
||||
uint8_t pc : 3;
|
||||
uint8_t reserved : 5;
|
||||
} Reg0B_Engine3PC;
|
||||
|
||||
typedef struct {
|
||||
bool ENG3_INT : 1;
|
||||
bool ENG2_INT : 1;
|
||||
bool ENG1_INT : 1;
|
||||
bool ENG3_INT : 1;
|
||||
bool ENG2_INT : 1;
|
||||
bool ENG1_INT : 1;
|
||||
bool EXT_CLK_USED : 1;
|
||||
uint8_t reserved : 5;
|
||||
uint8_t reserved : 5;
|
||||
} Reg0C_Status;
|
||||
|
||||
typedef struct {
|
||||
@@ -90,8 +90,8 @@ typedef enum {
|
||||
} EngSelect;
|
||||
|
||||
typedef struct {
|
||||
EngSelect blue : 2;
|
||||
EngSelect blue : 2;
|
||||
EngSelect green : 2;
|
||||
EngSelect red : 2;
|
||||
EngSelect red : 2;
|
||||
EngSelect white : 2;
|
||||
} Reg70_LedMap;
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ST25R3916_IRQ_MASK_ALL (uint32_t)(0xFFFFFFFFUL) /** All ST25R3916 interrupt sources */
|
||||
#define ST25R3916_IRQ_MASK_ALL (uint32_t)(0xFFFFFFFFUL) /** All ST25R3916 interrupt sources */
|
||||
#define ST25R3916_IRQ_MASK_NONE (uint32_t)(0x00000000UL) /**No ST25R3916 interrupt source */
|
||||
|
||||
/** Main interrupt register */
|
||||
|
||||
@@ -253,5 +253,5 @@ bool st25r3916_check_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t mask,
|
||||
|
||||
uint8_t reg_val = 0;
|
||||
st25r3916_read_reg(handle, reg, ®_val);
|
||||
return ((reg_val & mask) == val);
|
||||
return (reg_val & mask) == val;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user