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SubGhz: furi_hal_subghz remove preset load function by name

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This commit is contained in:
gid9798
2023-07-03 13:36:26 +03:00
parent 0d6e6c4d85
commit 01d7beef4e
17 changed files with 529 additions and 396 deletions
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2
applications/debug/unit_tests/subghz/subghz_test.c
View File

@@ -322,7 +322,7 @@ bool subghz_hal_async_tx_test_run(SubGhzHalAsyncTxTestType type) {
SubGhzHalAsyncTxTest test = {0};
test.type = type;
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok650Async);
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_ook_650khz_async_regs);
furi_hal_subghz_set_frequency_and_path(433920000);
if(!furi_hal_subghz_start_async_tx(subghz_hal_async_tx_test_yield, &test)) {

37
applications/drivers/subghz/cc1101_ext/cc1101_ext.c
View File

@@ -73,7 +73,6 @@ typedef struct {
typedef struct {
volatile SubGhzDeviceCC1101ExtState state;
volatile SubGhzDeviceCC1101ExtRegulation regulation;
volatile FuriHalSubGhzPreset preset;
const GpioPin* async_mirror_pin;
FuriHalSpiBusHandle* spi_bus_handle;
const GpioPin* g0_pin;
@@ -86,7 +85,6 @@ static SubGhzDeviceCC1101Ext* subghz_device_cc1101_ext = NULL;
static bool subghz_device_cc1101_ext_check_init() {
furi_assert(subghz_device_cc1101_ext->state == SubGhzDeviceCC1101ExtStateInit);
subghz_device_cc1101_ext->state = SubGhzDeviceCC1101ExtStateIdle;
subghz_device_cc1101_ext->preset = FuriHalSubGhzPresetIDLE;
bool ret = false;
@@ -163,7 +161,6 @@ bool subghz_device_cc1101_ext_alloc() {
subghz_device_cc1101_ext = malloc(sizeof(SubGhzDeviceCC1101Ext));
subghz_device_cc1101_ext->state = SubGhzDeviceCC1101ExtStateInit;
subghz_device_cc1101_ext->regulation = SubGhzDeviceCC1101ExtRegulationTxRx;
subghz_device_cc1101_ext->preset = FuriHalSubGhzPresetIDLE;
subghz_device_cc1101_ext->async_mirror_pin = NULL;
subghz_device_cc1101_ext->spi_bus_handle = &furi_hal_spi_bus_handle_external;
subghz_device_cc1101_ext->g0_pin = SUBGHZ_DEVICE_CC1101_EXT_TX_GPIO;
@@ -218,8 +215,6 @@ void subghz_device_cc1101_ext_sleep() {
cc1101_shutdown(subghz_device_cc1101_ext->spi_bus_handle);
furi_hal_spi_release(subghz_device_cc1101_ext->spi_bus_handle);
subghz_device_cc1101_ext->preset = FuriHalSubGhzPresetIDLE;
}
void subghz_device_cc1101_ext_dump_state() {
@@ -231,37 +226,6 @@ void subghz_device_cc1101_ext_dump_state() {
furi_hal_spi_release(subghz_device_cc1101_ext->spi_bus_handle);
}
void subghz_device_cc1101_ext_load_preset(FuriHalSubGhzPreset preset) {
if(preset == FuriHalSubGhzPresetOok650Async) {
subghz_device_cc1101_ext_load_registers(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
subghz_device_cc1101_ext_load_patable(subghz_device_cc1101_preset_ook_async_patable);
} else if(preset == FuriHalSubGhzPresetOok270Async) {
subghz_device_cc1101_ext_load_registers(
(uint8_t*)subghz_device_cc1101_preset_ook_270khz_async_regs);
subghz_device_cc1101_ext_load_patable(subghz_device_cc1101_preset_ook_async_patable);
} else if(preset == FuriHalSubGhzPreset2FSKDev238Async) {
subghz_device_cc1101_ext_load_registers(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs);
subghz_device_cc1101_ext_load_patable(subghz_device_cc1101_preset_2fsk_async_patable);
} else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
subghz_device_cc1101_ext_load_registers(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs);
subghz_device_cc1101_ext_load_patable(subghz_device_cc1101_preset_2fsk_async_patable);
} else if(preset == FuriHalSubGhzPresetMSK99_97KbAsync) {
subghz_device_cc1101_ext_load_registers(
(uint8_t*)subghz_device_cc1101_preset_msk_99_97kb_async_regs);
subghz_device_cc1101_ext_load_patable(subghz_device_cc1101_preset_msk_async_patable);
} else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
subghz_device_cc1101_ext_load_registers(
(uint8_t*)subghz_device_cc1101_preset_gfsk_9_99kb_async_regs);
subghz_device_cc1101_ext_load_patable(subghz_device_cc1101_preset_gfsk_async_patable);
} else {
furi_crash("SubGhz: Missing config.");
}
subghz_device_cc1101_ext->preset = preset;
}
void subghz_device_cc1101_ext_load_custom_preset(uint8_t* preset_data) {
//load config
furi_hal_spi_acquire(subghz_device_cc1101_ext->spi_bus_handle);
@@ -278,7 +242,6 @@ void subghz_device_cc1101_ext_load_custom_preset(uint8_t* preset_data) {
//load pa table
memcpy(&pa[0], &preset_data[i + 2], 8);
subghz_device_cc1101_ext_load_patable(pa);
subghz_device_cc1101_ext->preset = FuriHalSubGhzPresetCustom;
//show debug
if(furi_hal_rtc_is_flag_set(FuriHalRtcFlagDebug)) {

6
applications/drivers/subghz/cc1101_ext/cc1101_ext.h
View File

@@ -54,12 +54,6 @@ void subghz_device_cc1101_ext_sleep();
*/
void subghz_device_cc1101_ext_dump_state();
/** Load registers from preset by preset name
*
* @param preset to load
*/
void subghz_device_cc1101_ext_load_preset(FuriHalSubGhzPreset preset);
/** Load custom registers from preset
*
* @param preset_data registers to load

31
applications/drivers/subghz/cc1101_ext/cc1101_ext_interconnect.c
View File

@@ -1,5 +1,6 @@
#include "cc1101_ext_interconnect.h"
#include "cc1101_ext.h"
#include <lib/subghz/devices/cc1101_configs.h>
#define TAG "SubGhzDeviceCC1101Ext"
@@ -29,9 +30,33 @@ static void subghz_device_cc1101_ext_interconnect_start_async_rx(void* callback,
static void subghz_device_cc1101_ext_interconnect_load_preset(
FuriHalSubGhzPreset preset,
uint8_t* preset_data) {
if(preset != FuriHalSubGhzPresetCustom) {
subghz_device_cc1101_ext_load_preset(preset);
} else {
switch(preset) {
case FuriHalSubGhzPresetOok650Async:
subghz_device_cc1101_ext_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
break;
case FuriHalSubGhzPresetOok270Async:
subghz_device_cc1101_ext_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_270khz_async_regs);
break;
case FuriHalSubGhzPreset2FSKDev238Async:
subghz_device_cc1101_ext_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs);
break;
case FuriHalSubGhzPreset2FSKDev476Async:
subghz_device_cc1101_ext_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs);
break;
case FuriHalSubGhzPresetMSK99_97KbAsync:
subghz_device_cc1101_ext_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_msk_99_97kb_async_regs);
break;
case FuriHalSubGhzPresetGFSK9_99KbAsync:
subghz_device_cc1101_ext_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_gfsk_9_99kb_async_regs);
break;
default:
subghz_device_cc1101_ext_load_custom_preset(preset_data);
}
}

5
applications/main/subghz/helpers/subghz_txrx.c
View File

@@ -64,6 +64,7 @@ SubGhzTxRx* subghz_txrx_alloc() {
//set default device External
subghz_devices_init();
instance->radio_device_type = SubGhzRadioDeviceTypeInternal;
instance->radio_device_type =
subghz_txrx_radio_device_set(instance, SubGhzRadioDeviceTypeExternalCC1101);
@@ -604,9 +605,7 @@ SubGhzRadioDeviceType
} else {
subghz_txrx_radio_device_power_off(instance);
if(instance->radio_device_type != SubGhzRadioDeviceTypeInternal) {
if(instance->radio_device) {
subghz_devices_end(instance->radio_device);
}
subghz_devices_end(instance->radio_device);
}
instance->radio_device = subghz_devices_get_by_name(SUBGHZ_DEVICE_CC1101_INT_NAME);
instance->radio_device_type = SubGhzRadioDeviceTypeInternal;

10
applications/main/subghz/subghz_cli.c
View File

@@ -13,6 +13,7 @@
#include <applications/drivers/subghz/cc1101_ext/cc1101_ext_interconnect.h>
#include <lib/subghz/devices/cc1101_int/cc1101_int_interconnect.h>
#include <lib/subghz/devices/devices.h>
#include <lib/subghz/devices/cc1101_configs.h>
#include "helpers/subghz_chat.h"
@@ -60,7 +61,8 @@ void subghz_cli_command_tx_carrier(Cli* cli, FuriString* args, void* context) {
}
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok650Async);
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
frequency = furi_hal_subghz_set_frequency_and_path(frequency);
furi_hal_gpio_init(&gpio_cc1101_g0, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
@@ -104,7 +106,8 @@ void subghz_cli_command_rx_carrier(Cli* cli, FuriString* args, void* context) {
}
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok650Async);
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
frequency = furi_hal_subghz_set_frequency_and_path(frequency);
printf("Receiving at frequency %lu Hz\r\n", frequency);
printf("Press CTRL+C to stop\r\n");
@@ -400,7 +403,8 @@ void subghz_cli_command_rx_raw(Cli* cli, FuriString* args, void* context) {
// Configure radio
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok270Async);
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
frequency = furi_hal_subghz_set_frequency_and_path(frequency);
furi_hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullNo, GpioSpeedLow);

4
applications/main/subghz/views/subghz_test_carrier.c
View File

@@ -1,6 +1,7 @@
#include "subghz_test_carrier.h"
#include "../subghz_i.h"
#include "../helpers/subghz_testing.h"
#include <lib/subghz/devices/cc1101_configs.h>
#include <math.h>
#include <furi.h>
@@ -140,7 +141,8 @@ void subghz_test_carrier_enter(void* context) {
SubGhzTestCarrier* subghz_test_carrier = context;
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok650Async);
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
furi_hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullNo, GpioSpeedLow);

4
applications/main/subghz/views/subghz_test_packet.c
View File

@@ -1,6 +1,7 @@
#include "subghz_test_packet.h"
#include "../subghz_i.h"
#include "../helpers/subghz_testing.h"
#include <lib/subghz/devices/cc1101_configs.h>
#include <math.h>
#include <furi.h>
@@ -194,7 +195,8 @@ void subghz_test_packet_enter(void* context) {
SubGhzTestPacket* instance = context;
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok650Async);
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
with_view_model(
instance->view,

4
applications/main/subghz/views/subghz_test_static.c
View File

@@ -1,6 +1,7 @@
#include "subghz_test_static.h"
#include "../subghz_i.h"
#include "../helpers/subghz_testing.h"
#include <lib/subghz/devices/cc1101_configs.h>
#include <math.h>
#include <furi.h>
@@ -143,7 +144,8 @@ void subghz_test_static_enter(void* context) {
SubGhzTestStatic* instance = context;
furi_hal_subghz_reset();
furi_hal_subghz_load_preset(FuriHalSubGhzPresetOok650Async);
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
furi_hal_gpio_init(&gpio_cc1101_g0, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
furi_hal_gpio_write(&gpio_cc1101_g0, false);

10
firmware/targets/f7/api_symbols.csv
View File

@@ -1,5 +1,5 @@
entry,status,name,type,params
Version,+,32.0,,
Version,+,33.0,,
Header,+,applications/services/bt/bt_service/bt.h,,
Header,+,applications/services/cli/cli.h,,
Header,+,applications/services/cli/cli_vcp.h,,
@@ -185,6 +185,7 @@ Header,+,lib/subghz/blocks/decoder.h,,
Header,+,lib/subghz/blocks/encoder.h,,
Header,+,lib/subghz/blocks/generic.h,,
Header,+,lib/subghz/blocks/math.h,,
Header,+,lib/subghz/devices/cc1101_configs.h,,
Header,+,lib/subghz/environment.h,,
Header,+,lib/subghz/protocols/raw.h,,
Header,+,lib/subghz/receiver.h,,
@@ -1398,7 +1399,6 @@ Function,+,furi_hal_subghz_is_rx_data_crc_valid,_Bool,
Function,+,furi_hal_subghz_is_tx_allowed,_Bool,uint32_t
Function,+,furi_hal_subghz_load_custom_preset,void,uint8_t*
Function,+,furi_hal_subghz_load_patable,void,const uint8_t[8]
Function,+,furi_hal_subghz_load_preset,void,FuriHalSubGhzPreset
Function,+,furi_hal_subghz_load_registers,void,uint8_t*
Function,+,furi_hal_subghz_read_packet,void,"uint8_t*, uint8_t*"
Function,+,furi_hal_subghz_reset,void,
@@ -3443,6 +3443,12 @@ Variable,+,sequence_set_vibro_on,const NotificationSequence,
Variable,+,sequence_single_vibro,const NotificationSequence,
Variable,+,sequence_solid_yellow,const NotificationSequence,
Variable,+,sequence_success,const NotificationSequence,
Variable,+,subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs,const uint8_t[],
Variable,+,subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs,const uint8_t[],
Variable,+,subghz_device_cc1101_preset_gfsk_9_99kb_async_regs,const uint8_t[],
Variable,+,subghz_device_cc1101_preset_msk_99_97kb_async_regs,const uint8_t[],
Variable,+,subghz_device_cc1101_preset_ook_270khz_async_regs,const uint8_t[],
Variable,+,subghz_device_cc1101_preset_ook_650khz_async_regs,const uint8_t[],
Variable,+,subghz_protocol_raw,const SubGhzProtocol,
Variable,+,subghz_protocol_raw_decoder,const SubGhzProtocolDecoder,
Variable,+,subghz_protocol_raw_encoder,const SubGhzProtocolEncoder,
1 entry status name type params
2 Version + 32.0 33.0
3 Header + applications/services/bt/bt_service/bt.h
4 Header + applications/services/cli/cli.h
5 Header + applications/services/cli/cli_vcp.h
185 Header + lib/subghz/blocks/encoder.h
186 Header + lib/subghz/blocks/generic.h
187 Header + lib/subghz/blocks/math.h
188 Header + lib/subghz/devices/cc1101_configs.h
189 Header + lib/subghz/environment.h
190 Header + lib/subghz/protocols/raw.h
191 Header + lib/subghz/receiver.h
1399 Function + furi_hal_subghz_is_tx_allowed _Bool uint32_t
1400 Function + furi_hal_subghz_load_custom_preset void uint8_t*
1401 Function + furi_hal_subghz_load_patable void const uint8_t[8]
Function + furi_hal_subghz_load_preset void FuriHalSubGhzPreset
1402 Function + furi_hal_subghz_load_registers void uint8_t*
1403 Function + furi_hal_subghz_read_packet void uint8_t*, uint8_t*
1404 Function + furi_hal_subghz_reset void
3443 Variable + sequence_single_vibro const NotificationSequence
3444 Variable + sequence_solid_yellow const NotificationSequence
3445 Variable + sequence_success const NotificationSequence
3446 Variable + subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs const uint8_t[]
3447 Variable + subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs const uint8_t[]
3448 Variable + subghz_device_cc1101_preset_gfsk_9_99kb_async_regs const uint8_t[]
3449 Variable + subghz_device_cc1101_preset_msk_99_97kb_async_regs const uint8_t[]
3450 Variable + subghz_device_cc1101_preset_ook_270khz_async_regs const uint8_t[]
3451 Variable + subghz_device_cc1101_preset_ook_650khz_async_regs const uint8_t[]
3452 Variable + subghz_protocol_raw const SubGhzProtocol
3453 Variable + subghz_protocol_raw_decoder const SubGhzProtocolDecoder
3454 Variable + subghz_protocol_raw_encoder const SubGhzProtocolEncoder

37
firmware/targets/f7/furi_hal/furi_hal_subghz.c
View File

@@ -50,7 +50,6 @@ typedef enum {
typedef struct {
volatile SubGhzState state;
volatile SubGhzRegulation regulation;
volatile FuriHalSubGhzPreset preset;
const GpioPin* async_mirror_pin;
uint8_t rolling_counter_mult;
@@ -61,7 +60,6 @@ typedef struct {
volatile FuriHalSubGhz furi_hal_subghz = {
.state = SubGhzStateInit,
.regulation = SubGhzRegulationTxRx,
.preset = FuriHalSubGhzPresetIDLE,
.async_mirror_pin = NULL,
.rolling_counter_mult = 1,
.dangerous_frequency_i = false,
@@ -90,7 +88,6 @@ const GpioPin* furi_hal_subghz_get_data_gpio() {
void furi_hal_subghz_init() {
furi_assert(furi_hal_subghz.state == SubGhzStateInit);
furi_hal_subghz.state = SubGhzStateIdle;
furi_hal_subghz.preset = FuriHalSubGhzPresetIDLE;
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
@@ -144,8 +141,6 @@ void furi_hal_subghz_sleep() {
cc1101_shutdown(&furi_hal_spi_bus_handle_subghz);
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
furi_hal_subghz.preset = FuriHalSubGhzPresetIDLE;
}
void furi_hal_subghz_dump_state() {
@@ -157,37 +152,6 @@ void furi_hal_subghz_dump_state() {
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
}
void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
if(preset == FuriHalSubGhzPresetOok650Async) {
furi_hal_subghz_load_registers(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
furi_hal_subghz_load_patable(subghz_device_cc1101_preset_ook_async_patable);
} else if(preset == FuriHalSubGhzPresetOok270Async) {
furi_hal_subghz_load_registers(
(uint8_t*)subghz_device_cc1101_preset_ook_270khz_async_regs);
furi_hal_subghz_load_patable(subghz_device_cc1101_preset_ook_async_patable);
} else if(preset == FuriHalSubGhzPreset2FSKDev238Async) {
furi_hal_subghz_load_registers(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs);
furi_hal_subghz_load_patable(subghz_device_cc1101_preset_2fsk_async_patable);
} else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
furi_hal_subghz_load_registers(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs);
furi_hal_subghz_load_patable(subghz_device_cc1101_preset_2fsk_async_patable);
} else if(preset == FuriHalSubGhzPresetMSK99_97KbAsync) {
furi_hal_subghz_load_registers(
(uint8_t*)subghz_device_cc1101_preset_msk_99_97kb_async_regs);
furi_hal_subghz_load_patable(subghz_device_cc1101_preset_msk_async_patable);
} else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
furi_hal_subghz_load_registers(
(uint8_t*)subghz_device_cc1101_preset_gfsk_9_99kb_async_regs);
furi_hal_subghz_load_patable(subghz_device_cc1101_preset_gfsk_async_patable);
} else {
furi_crash("SubGhz: Missing config.");
}
furi_hal_subghz.preset = preset;
}
void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
//load config
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
@@ -203,7 +167,6 @@ void furi_hal_subghz_load_custom_preset(uint8_t* preset_data) {
//load pa table
memcpy(&pa[0], &preset_data[i + 2], 8);
furi_hal_subghz_load_patable(pa);
furi_hal_subghz.preset = FuriHalSubGhzPresetCustom;
//show debug
if(furi_hal_rtc_is_flag_set(FuriHalRtcFlagDebug)) {

6
firmware/targets/f7/furi_hal/furi_hal_subghz.h
View File

@@ -60,12 +60,6 @@ void furi_hal_subghz_sleep();
*/
void furi_hal_subghz_dump_state();
/** Load registers from preset by preset name
*
* @param preset to load
*/
void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset);
/** Load custom registers from preset
*
* @param preset_data registers to load

1
lib/subghz/SConscript
View File

@@ -19,6 +19,7 @@ env.Append(
File("blocks/math.h"),
File("subghz_setting.h"),
File("subghz_protocol_registry.h"),
File("devices/cc1101_configs.h"),
],
)

679
lib/subghz/devices/cc1101_configs.c
View File

@@ -1,268 +1,68 @@
#include "cc1101_configs.h"
#include <cc1101_regs.h>
const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[][2] = {
const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
CC1101_IOCFG0,
0x0D, // GD0 as async serial data output/input
/* FIFO and internals */
{CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
CC1101_FIFOTHR,
0x47, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
CC1101_PKTCTRL0,
0x32, // Async, continious, no whitening
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
CC1101_FSCTRL1,
0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
{CC1101_MDMCFG4, 0x67}, // Rx BW filter is 270.833333kHz
CC1101_MDMCFG0,
0x00, // Channel spacing is 25kHz
CC1101_MDMCFG1,
0x00, // Channel spacing is 25kHz
CC1101_MDMCFG2,
0x30, // Format ASK/OOK, No preamble/sync
CC1101_MDMCFG3,
0x32, // Data rate is 3.79372 kBaud
CC1101_MDMCFG4,
0x67, // Rx BW filter is 270.833333kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
CC1101_MCSM0,
0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
CC1101_FOCCFG,
0x18, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{CC1101_AGCCTRL0,
0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
{CC1101_AGCCTRL1,
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
CC1101_AGCCTRL0,
0x40, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
CC1101_AGCCTRL1,
0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
CC1101_AGCCTRL2,
0x03, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
CC1101_WORCTRL,
0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
{CC1101_FREND1, 0xB6}, //
CC1101_FREND0,
0x11, // Adjusts current TX LO buffer + high is PATABLE[1]
CC1101_FREND1,
0xB6, //
/* End */
{0, 0},
};
/* End load reg */
0,
0,
const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[][2] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* FIFO and internals */
{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
{CC1101_MDMCFG4, 0x17}, // Rx BW filter is 650.000kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
// {CC1101_AGCTRL0,0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
// {CC1101_AGCTRL1,0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
// {CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
{CC1101_AGCCTRL0,
0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
{CC1101_AGCCTRL1,
0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
{CC1101_FREND1, 0xB6}, //
/* End */
{0, 0},
};
const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[][2] = {
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
{CC1101_PKTCTRL1, 0x04},
// // Modem Configuration
{CC1101_MDMCFG0, 0x00},
{CC1101_MDMCFG1, 0x02},
{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
{CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{CC1101_AGCCTRL0,
0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
{CC1101_AGCCTRL1,
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
{CC1101_FREND1, 0x56},
/* End */
{0, 0},
};
const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[][2] = {
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
{CC1101_PKTCTRL1, 0x04},
// // Modem Configuration
{CC1101_MDMCFG0, 0x00},
{CC1101_MDMCFG1, 0x02},
{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
{CC1101_DEVIATN, 0x47}, //Deviation 47.60742 kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{CC1101_AGCCTRL0,
0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
{CC1101_AGCCTRL1,
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
{CC1101_FREND1, 0x56},
/* End */
{0, 0},
};
const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[][2] = {
/* GPIO GD0 */
{CC1101_IOCFG0, 0x06},
{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
{CC1101_SYNC1, 0x46},
{CC1101_SYNC0, 0x4C},
{CC1101_ADDR, 0x00},
{CC1101_PKTLEN, 0x00},
{CC1101_CHANNR, 0x00},
{CC1101_PKTCTRL0, 0x05},
{CC1101_FSCTRL0, 0x23},
{CC1101_FSCTRL1, 0x06},
{CC1101_MDMCFG0, 0xF8},
{CC1101_MDMCFG1, 0x22},
{CC1101_MDMCFG2, 0x72},
{CC1101_MDMCFG3, 0xF8},
{CC1101_MDMCFG4, 0x5B},
{CC1101_DEVIATN, 0x47},
{CC1101_MCSM0, 0x18},
{CC1101_FOCCFG, 0x16},
{CC1101_AGCCTRL0, 0xB2},
{CC1101_AGCCTRL1, 0x00},
{CC1101_AGCCTRL2, 0xC7},
{CC1101_FREND0, 0x10},
{CC1101_FREND1, 0x56},
{CC1101_BSCFG, 0x1C},
{CC1101_FSTEST, 0x59},
/* End */
{0, 0},
};
const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[][2] = {
{CC1101_IOCFG0, 0x06}, //GDO0 Output Pin Configuration
{CC1101_FIFOTHR, 0x47}, //RX FIFO and TX FIFO Thresholds
//1 : CRC calculation in TX and CRC check in RX enabled,
//1 : Variable packet length mode. Packet length configured by the first byte after sync word
{CC1101_PKTCTRL0, 0x05},
{CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control
{CC1101_SYNC1, 0x46},
{CC1101_SYNC0, 0x4C},
{CC1101_ADDR, 0x00},
{CC1101_PKTLEN, 0x00},
{CC1101_MDMCFG4, 0xC8}, //Modem Configuration 9.99
{CC1101_MDMCFG3, 0x93}, //Modem Configuration
{CC1101_MDMCFG2, 0x12}, // 2: 16/16 sync word bits detected
{CC1101_DEVIATN, 0x34}, //Deviation = 19.042969
{CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
{CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration
{CC1101_AGCCTRL2, 0x43}, //AGC Control
{CC1101_AGCCTRL1, 0x40},
{CC1101_AGCCTRL0, 0x91},
{CC1101_WORCTRL, 0xFB}, //Wake On Radio Control
/* End */
{0, 0},
};
const uint8_t subghz_device_cc1101_preset_ook_async_patable[8] = {
//ook_async_patable[8]
0x00,
0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
0x00,
@@ -270,19 +70,146 @@ const uint8_t subghz_device_cc1101_preset_ook_async_patable[8] = {
0x00,
0x00,
0x00,
0x00};
0x00,
};
const uint8_t subghz_device_cc1101_preset_ook_async_patable_au[8] = {
0x00,
0x37, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};
const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8] = {
/* GPIO GD0 */
CC1101_IOCFG0,
0x0D, // GD0 as async serial data output/input
/* FIFO and internals */
CC1101_FIFOTHR,
0x07, // The only important bit is ADC_RETENTION
/* Packet engine */
CC1101_PKTCTRL0,
0x32, // Async, continious, no whitening
/* Frequency Synthesizer Control */
CC1101_FSCTRL1,
0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
CC1101_MDMCFG0,
0x00, // Channel spacing is 25kHz
CC1101_MDMCFG1,
0x00, // Channel spacing is 25kHz
CC1101_MDMCFG2,
0x30, // Format ASK/OOK, No preamble/sync
CC1101_MDMCFG3,
0x32, // Data rate is 3.79372 kBaud
CC1101_MDMCFG4,
0x17, // Rx BW filter is 650.000kHz
/* Main Radio Control State Machine */
CC1101_MCSM0,
0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
CC1101_FOCCFG,
0x18, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
// CC1101_AGCTRL0,0x40, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
// CC1101_AGCTRL1,0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
// CC1101_AGCCTRL2, 0x03, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
CC1101_AGCCTRL0,
0x91, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
CC1101_AGCCTRL1,
0x0, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
CC1101_AGCCTRL2,
0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
CC1101_WORCTRL,
0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
CC1101_FREND0,
0x11, // Adjusts current TX LO buffer + high is PATABLE[1]
CC1101_FREND1,
0xB6, //
/* End load reg */
0,
0,
//ook_async_patable[8]
0x00,
0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[] = {
/* GPIO GD0 */
CC1101_IOCFG0,
0x0D, // GD0 as async serial data output/input
/* Frequency Synthesizer Control */
CC1101_FSCTRL1,
0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
/* Packet engine */
CC1101_PKTCTRL0,
0x32, // Async, continious, no whitening
CC1101_PKTCTRL1,
0x04,
// // Modem Configuration
CC1101_MDMCFG0,
0x00,
CC1101_MDMCFG1,
0x02,
CC1101_MDMCFG2,
0x04, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
CC1101_MDMCFG3,
0x83, // Data rate is 4.79794 kBaud
CC1101_MDMCFG4,
0x67, //Rx BW filter is 270.833333 kHz
CC1101_DEVIATN,
0x04, //Deviation 2.380371 kHz
/* Main Radio Control State Machine */
CC1101_MCSM0,
0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
CC1101_FOCCFG,
0x16, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
CC1101_AGCCTRL0,
0x91, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
CC1101_AGCCTRL1,
0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
CC1101_AGCCTRL2,
0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
CC1101_WORCTRL,
0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
CC1101_FREND0,
0x10, // Adjusts current TX LO buffer
CC1101_FREND1,
0x56,
/* End load reg */
0,
0,
// 2fsk_async_patable[8]
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
@@ -290,9 +217,70 @@ const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8] = {
0x00,
0x00,
0x00,
0x00};
0x00,
};
const uint8_t subghz_device_cc1101_preset_msk_async_patable[8] = {
const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[] = {
/* GPIO GD0 */
CC1101_IOCFG0,
0x0D, // GD0 as async serial data output/input
/* Frequency Synthesizer Control */
CC1101_FSCTRL1,
0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
/* Packet engine */
CC1101_PKTCTRL0,
0x32, // Async, continious, no whitening
CC1101_PKTCTRL1,
0x04,
// // Modem Configuration
CC1101_MDMCFG0,
0x00,
CC1101_MDMCFG1,
0x02,
CC1101_MDMCFG2,
0x04, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
CC1101_MDMCFG3,
0x83, // Data rate is 4.79794 kBaud
CC1101_MDMCFG4,
0x67, //Rx BW filter is 270.833333 kHz
CC1101_DEVIATN,
0x47, //Deviation 47.60742 kHz
/* Main Radio Control State Machine */
CC1101_MCSM0,
0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
CC1101_FOCCFG,
0x16, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
CC1101_AGCCTRL0,
0x91, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
CC1101_AGCCTRL1,
0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
CC1101_AGCCTRL2,
0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
CC1101_WORCTRL,
0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
CC1101_FREND0,
0x10, // Adjusts current TX LO buffer
CC1101_FREND1,
0x56,
/* End load reg */
0,
0,
// 2fsk_async_patable[8]
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
@@ -300,9 +288,75 @@ const uint8_t subghz_device_cc1101_preset_msk_async_patable[8] = {
0x00,
0x00,
0x00,
0x00};
0x00,
};
const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8] = {
const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[] = {
/* GPIO GD0 */
CC1101_IOCFG0,
0x06,
CC1101_FIFOTHR,
0x07, // The only important bit is ADC_RETENTION
CC1101_SYNC1,
0x46,
CC1101_SYNC0,
0x4C,
CC1101_ADDR,
0x00,
CC1101_PKTLEN,
0x00,
CC1101_CHANNR,
0x00,
CC1101_PKTCTRL0,
0x05,
CC1101_FSCTRL0,
0x23,
CC1101_FSCTRL1,
0x06,
CC1101_MDMCFG0,
0xF8,
CC1101_MDMCFG1,
0x22,
CC1101_MDMCFG2,
0x72,
CC1101_MDMCFG3,
0xF8,
CC1101_MDMCFG4,
0x5B,
CC1101_DEVIATN,
0x47,
CC1101_MCSM0,
0x18,
CC1101_FOCCFG,
0x16,
CC1101_AGCCTRL0,
0xB2,
CC1101_AGCCTRL1,
0x00,
CC1101_AGCCTRL2,
0xC7,
CC1101_FREND0,
0x10,
CC1101_FREND1,
0x56,
CC1101_BSCFG,
0x1C,
CC1101_FSTEST,
0x59,
/* End load reg */
0,
0,
// msk_async_patable[8]
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
@@ -310,4 +364,119 @@ const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8] = {
0x00,
0x00,
0x00,
0x00};
0x00,
};
const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[] = {
CC1101_IOCFG0,
0x06, //GDO0 Output Pin Configuration
CC1101_FIFOTHR,
0x47, //RX FIFO and TX FIFO Thresholds
//1 : CRC calculation in TX and CRC check in RX enabled,
//1 : Variable packet length mode. Packet length configured by the first byte after sync word
CC1101_PKTCTRL0,
0x05,
CC1101_FSCTRL1,
0x06, //Frequency Synthesizer Control
CC1101_SYNC1,
0x46,
CC1101_SYNC0,
0x4C,
CC1101_ADDR,
0x00,
CC1101_PKTLEN,
0x00,
CC1101_MDMCFG4,
0xC8, //Modem Configuration 9.99
CC1101_MDMCFG3,
0x93, //Modem Configuration
CC1101_MDMCFG2,
0x12, // 2: 16/16 sync word bits detected
CC1101_DEVIATN,
0x34, //Deviation = 19.042969
CC1101_MCSM0,
0x18, //Main Radio Control State Machine Configuration
CC1101_FOCCFG,
0x16, //Frequency Offset Compensation Configuration
CC1101_AGCCTRL2,
0x43, //AGC Control
CC1101_AGCCTRL1,
0x40,
CC1101_AGCCTRL0,
0x91,
CC1101_WORCTRL,
0xFB, //Wake On Radio Control
/* End load reg */
0,
0,
// gfsk_async_patable[8]
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
// Shpargalka
// const uint8_t subghz_device_cc1101_preset_ook_async_patable[8] = {
// 0x00,
// 0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00};
// const uint8_t subghz_device_cc1101_preset_ook_async_patable_au[8] = {
// 0x00,
// 0x37, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00};
// const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8] = {
// 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00};
// const uint8_t subghz_device_cc1101_preset_msk_async_patable[8] = {
// 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00};
// const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8] = {
// 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00,
// 0x00};

23
lib/subghz/devices/cc1101_configs.h
View File

@@ -5,17 +5,18 @@
extern "C" {
#endif
extern const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[][2];
extern const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[][2];
extern const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[][2];
extern const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[][2];
extern const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[][2];
extern const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[][2];
extern const uint8_t subghz_device_cc1101_preset_ook_async_patable[8];
extern const uint8_t subghz_device_cc1101_preset_ook_async_patable_au[8];
extern const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8];
extern const uint8_t subghz_device_cc1101_preset_msk_async_patable[8];
extern const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8];
extern const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[];
extern const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[];
extern const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[];
extern const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[];
extern const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[];
extern const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[];
// extern const uint8_t subghz_device_cc1101_preset_ook_async_patable[8];
// extern const uint8_t subghz_device_cc1101_preset_ook_async_patable_au[8];
// extern const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8];
// extern const uint8_t subghz_device_cc1101_preset_msk_async_patable[8];
// extern const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8];
#ifdef __cplusplus
}

37
lib/subghz/devices/cc1101_int/cc1101_int_interconnect.c
View File

@@ -1,5 +1,6 @@
#include "cc1101_int_interconnect.h"
#include <furi_hal.h>
#include "../cc1101_configs.h"
#define TAG "SubGhzDeviceCC1101Int"
@@ -17,21 +18,43 @@ static uint32_t subghz_device_cc1101_int_interconnect_set_frequency(uint32_t fre
}
static bool subghz_device_cc1101_int_interconnect_start_async_tx(void* callback, void* context) {
return furi_hal_subghz_start_async_tx(
(FuriHalSubGhzAsyncTxCallback)callback, context);
return furi_hal_subghz_start_async_tx((FuriHalSubGhzAsyncTxCallback)callback, context);
}
static void subghz_device_cc1101_int_interconnect_start_async_rx(void* callback, void* context) {
furi_hal_subghz_start_async_rx(
(FuriHalSubGhzCaptureCallback)callback, context);
furi_hal_subghz_start_async_rx((FuriHalSubGhzCaptureCallback)callback, context);
}
static void subghz_device_cc1101_int_interconnect_load_preset(
FuriHalSubGhzPreset preset,
uint8_t* preset_data) {
if(preset != FuriHalSubGhzPresetCustom) {
furi_hal_subghz_load_preset(preset);
} else {
switch(preset) {
case FuriHalSubGhzPresetOok650Async:
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs);
break;
case FuriHalSubGhzPresetOok270Async:
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_ook_270khz_async_regs);
break;
case FuriHalSubGhzPreset2FSKDev238Async:
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs);
break;
case FuriHalSubGhzPreset2FSKDev476Async:
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs);
break;
case FuriHalSubGhzPresetMSK99_97KbAsync:
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_msk_99_97kb_async_regs);
break;
case FuriHalSubGhzPresetGFSK9_99KbAsync:
furi_hal_subghz_load_custom_preset(
(uint8_t*)subghz_device_cc1101_preset_gfsk_9_99kb_async_regs);
break;
default:
furi_hal_subghz_load_custom_preset(preset_data);
}
}

29
lib/subghz/subghz_setting.c
View File

@@ -149,8 +149,7 @@ void subghz_setting_free(SubGhzSetting* instance) {
static void subghz_setting_load_default_preset(
SubGhzSetting* instance,
const char* preset_name,
const uint8_t* preset_data,
const uint8_t preset_pa_table[8]) {
const uint8_t* preset_data) {
furi_assert(instance);
furi_assert(preset_data);
uint32_t preset_data_count = 0;
@@ -166,10 +165,8 @@ static void subghz_setting_load_default_preset(
preset_data_count += 2;
item->custom_preset_data_size = sizeof(uint8_t) * preset_data_count + sizeof(uint8_t) * 8;
item->custom_preset_data = malloc(item->custom_preset_data_size);
//load preset register
memcpy(&item->custom_preset_data[0], &preset_data[0], preset_data_count);
//load pa table
memcpy(&item->custom_preset_data[preset_data_count], &preset_pa_table[0], 8);
//load preset register + pa table
memcpy(&item->custom_preset_data[0], &preset_data[0], item->custom_preset_data_size);
}
static void subghz_setting_load_default_region(
@@ -193,25 +190,13 @@ static void subghz_setting_load_default_region(
}
subghz_setting_load_default_preset(
instance,
"AM270",
(uint8_t*)subghz_device_cc1101_preset_ook_270khz_async_regs,
subghz_device_cc1101_preset_ook_async_patable);
instance, "AM270", subghz_device_cc1101_preset_ook_270khz_async_regs);
subghz_setting_load_default_preset(
instance,
"AM650",
(uint8_t*)subghz_device_cc1101_preset_ook_650khz_async_regs,
subghz_device_cc1101_preset_ook_async_patable);
instance, "AM650", subghz_device_cc1101_preset_ook_650khz_async_regs);
subghz_setting_load_default_preset(
instance,
"FM238",
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs,
subghz_device_cc1101_preset_2fsk_async_patable);
instance, "FM238", subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs);
subghz_setting_load_default_preset(
instance,
"FM476",
(uint8_t*)subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs,
subghz_device_cc1101_preset_2fsk_async_patable);
instance, "FM476", subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs);
}
// Region check removed