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This commit is contained in:
gid9798
2023-06-18 20:25:16 +03:00
parent a191631c32
commit 3000b8fd0d
12 changed files with 912 additions and 14 deletions
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28
firmware/targets/f7/furi_hal/furi_hal_spi.c
View File

@@ -12,10 +12,10 @@
#define TAG "FuriHalSpi"
#define SPI_DMA DMA2
#define SPI_DMA_RX_CHANNEL LL_DMA_CHANNEL_3
#define SPI_DMA_TX_CHANNEL LL_DMA_CHANNEL_4
#define SPI_DMA_RX_IRQ FuriHalInterruptIdDma2Ch3
#define SPI_DMA_TX_IRQ FuriHalInterruptIdDma2Ch4
#define SPI_DMA_RX_CHANNEL LL_DMA_CHANNEL_6
#define SPI_DMA_TX_CHANNEL LL_DMA_CHANNEL_7
#define SPI_DMA_RX_IRQ FuriHalInterruptIdDma2Ch6
#define SPI_DMA_TX_IRQ FuriHalInterruptIdDma2Ch7
#define SPI_DMA_RX_DEF SPI_DMA, SPI_DMA_RX_CHANNEL
#define SPI_DMA_TX_DEF SPI_DMA, SPI_DMA_TX_CHANNEL
@@ -170,18 +170,18 @@ bool furi_hal_spi_bus_trx(
}
static void spi_dma_isr() {
#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_3
if(LL_DMA_IsActiveFlag_TC3(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_RX_DEF)) {
LL_DMA_ClearFlag_TC3(SPI_DMA);
#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_6
if(LL_DMA_IsActiveFlag_TC6(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_RX_DEF)) {
LL_DMA_ClearFlag_TC6(SPI_DMA);
furi_check(furi_semaphore_release(spi_dma_completed) == FuriStatusOk);
}
#else
#error Update this code. Would you kindly?
#endif
#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_4
if(LL_DMA_IsActiveFlag_TC4(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_TX_DEF)) {
LL_DMA_ClearFlag_TC4(SPI_DMA);
#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_7
if(LL_DMA_IsActiveFlag_TC7(SPI_DMA) && LL_DMA_IsEnabledIT_TC(SPI_DMA_TX_DEF)) {
LL_DMA_ClearFlag_TC7(SPI_DMA);
furi_check(furi_semaphore_release(spi_dma_completed) == FuriStatusOk);
}
#else
@@ -241,8 +241,8 @@ bool furi_hal_spi_bus_trx_dma(
dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
LL_DMA_Init(SPI_DMA_TX_DEF, &dma_config);
#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_4
LL_DMA_ClearFlag_TC4(SPI_DMA);
#if SPI_DMA_TX_CHANNEL == LL_DMA_CHANNEL_7
LL_DMA_ClearFlag_TC7(SPI_DMA);
#else
#error Update this code. Would you kindly?
#endif
@@ -315,8 +315,8 @@ bool furi_hal_spi_bus_trx_dma(
dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
LL_DMA_Init(SPI_DMA_RX_DEF, &dma_config);
#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_3
LL_DMA_ClearFlag_TC3(SPI_DMA);
#if SPI_DMA_RX_CHANNEL == LL_DMA_CHANNEL_6
LL_DMA_ClearFlag_TC6(SPI_DMA);
#else
#error Update this code. Would you kindly?
#endif

2
firmware/targets/f7/platform_specific/intrinsic_export.h
View File

@@ -1,10 +1,12 @@
#include <errno.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
void __clear_cache(void*, void*);
void* __aeabi_uldivmod(uint64_t, uint64_t);
#ifdef __cplusplus
}

314
lib/subghz/devices/cc1101_configs.h Normal file
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@@ -0,0 +1,314 @@
#pragma once
#include <cc1101.h>
static const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[][2] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* FIFO and internals */
{CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
{CC1101_MDMCFG4, 0x67}, // Rx BW filter is 270.833333kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{CC1101_AGCCTRL0,
0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
{CC1101_AGCCTRL1,
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
{CC1101_FREND1, 0xB6}, //
/* End */
{0, 0},
};
static const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[][2] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* FIFO and internals */
{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
{CC1101_MDMCFG4, 0x17}, // Rx BW filter is 650.000kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
// {CC1101_AGCTRL0,0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
// {CC1101_AGCTRL1,0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
// {CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
{CC1101_AGCCTRL0,
0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
{CC1101_AGCCTRL1,
0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
{CC1101_FREND1, 0xB6}, //
/* End */
{0, 0},
};
static const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[][2] = {
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
{CC1101_PKTCTRL1, 0x04},
// // Modem Configuration
{CC1101_MDMCFG0, 0x00},
{CC1101_MDMCFG1, 0x02},
{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
{CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{CC1101_AGCCTRL0,
0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
{CC1101_AGCCTRL1,
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
{CC1101_FREND1, 0x56},
/* End */
{0, 0},
};
static const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[][2] = {
/* GPIO GD0 */
{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
/* Frequency Synthesizer Control */
{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
/* Packet engine */
{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
{CC1101_PKTCTRL1, 0x04},
// // Modem Configuration
{CC1101_MDMCFG0, 0x00},
{CC1101_MDMCFG1, 0x02},
{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
{CC1101_DEVIATN, 0x47}, //Deviation 47.60742 kHz
/* Main Radio Control State Machine */
{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{CC1101_FOCCFG,
0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{CC1101_AGCCTRL0,
0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
{CC1101_AGCCTRL1,
0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
/* Wake on radio and timeouts control */
{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
{CC1101_FREND1, 0x56},
/* End */
{0, 0},
};
static const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[][2] = {
/* GPIO GD0 */
{CC1101_IOCFG0, 0x06},
{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
{CC1101_SYNC1, 0x46},
{CC1101_SYNC0, 0x4C},
{CC1101_ADDR, 0x00},
{CC1101_PKTLEN, 0x00},
{CC1101_CHANNR, 0x00},
{CC1101_PKTCTRL0, 0x05},
{CC1101_FSCTRL0, 0x23},
{CC1101_FSCTRL1, 0x06},
{CC1101_MDMCFG0, 0xF8},
{CC1101_MDMCFG1, 0x22},
{CC1101_MDMCFG2, 0x72},
{CC1101_MDMCFG3, 0xF8},
{CC1101_MDMCFG4, 0x5B},
{CC1101_DEVIATN, 0x47},
{CC1101_MCSM0, 0x18},
{CC1101_FOCCFG, 0x16},
{CC1101_AGCCTRL0, 0xB2},
{CC1101_AGCCTRL1, 0x00},
{CC1101_AGCCTRL2, 0xC7},
{CC1101_FREND0, 0x10},
{CC1101_FREND1, 0x56},
{CC1101_BSCFG, 0x1C},
{CC1101_FSTEST, 0x59},
/* End */
{0, 0},
};
static const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[][2] = {
{CC1101_IOCFG0, 0x06}, //GDO0 Output Pin Configuration
{CC1101_FIFOTHR, 0x47}, //RX FIFO and TX FIFO Thresholds
//1 : CRC calculation in TX and CRC check in RX enabled,
//1 : Variable packet length mode. Packet length configured by the first byte after sync word
{CC1101_PKTCTRL0, 0x05},
{CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control
{CC1101_SYNC1, 0x46},
{CC1101_SYNC0, 0x4C},
{CC1101_ADDR, 0x00},
{CC1101_PKTLEN, 0x00},
{CC1101_MDMCFG4, 0xC8}, //Modem Configuration 9.99
{CC1101_MDMCFG3, 0x93}, //Modem Configuration
{CC1101_MDMCFG2, 0x12}, // 2: 16/16 sync word bits detected
{CC1101_DEVIATN, 0x34}, //Deviation = 19.042969
{CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
{CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration
{CC1101_AGCCTRL2, 0x43}, //AGC Control
{CC1101_AGCCTRL1, 0x40},
{CC1101_AGCCTRL0, 0x91},
{CC1101_WORCTRL, 0xFB}, //Wake On Radio Control
/* End */
{0, 0},
};
static const uint8_t subghz_device_cc1101_preset_ook_async_patable[8] = {
0x00,
0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};
static const uint8_t subghz_device_cc1101_preset_ook_async_patable_au[8] = {
0x00,
0x37, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};
static const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8] = {
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};
static const uint8_t subghz_device_cc1101_preset_msk_async_patable[8] = {
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};
static const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8] = {
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};

79
lib/subghz/devices/cc1101_int/cc1101_int_interconnect.c Normal file
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@@ -0,0 +1,79 @@
#include "cc1101_int_interconnect.h"
#include <furi_hal.h>
#define TAG "SubGhzDeviceCC1101Int"
static bool subghz_device_cc1101_int_interconnect_is_frequency_valid(uint32_t frequency) {
bool ret = furi_hal_subghz_is_frequency_valid(frequency);
if(!ret) {
furi_crash("SubGhz: Incorrect frequency.");
}
return ret;
}
static uint32_t subghz_device_cc1101_int_interconnect_set_frequency(uint32_t frequency) {
subghz_device_cc1101_int_interconnect_is_frequency_valid(frequency);
return furi_hal_subghz_set_frequency_and_path(frequency);
}
static bool subghz_device_cc1101_int_interconnect_start_async_tx(void* callback, void* context) {
return furi_hal_subghz_start_async_tx(
(FuriHalSubGhzAsyncTxCallback)callback, context);
}
static void subghz_device_cc1101_int_interconnect_start_async_rx(void* callback, void* context) {
furi_hal_subghz_start_async_rx(
(FuriHalSubGhzCaptureCallback)callback, context);
}
static void subghz_device_cc1101_int_interconnect_load_preset(
FuriHalSubGhzPreset preset,
uint8_t* preset_data) {
if(preset != FuriHalSubGhzPresetCustom) {
furi_hal_subghz_load_preset(preset);
} else {
furi_hal_subghz_load_custom_preset(preset_data);
}
}
static bool subghz_device_cc1101_int_interconnect_is_connect(void) {
return true;
}
const SubGhzDeviceInterconnect subghz_device_cc1101_int_interconnect = {
.begin = NULL,
.end = furi_hal_subghz_shutdown,
.is_connect = subghz_device_cc1101_int_interconnect_is_connect,
.reset = furi_hal_subghz_reset,
.sleep = furi_hal_subghz_sleep,
.idle = furi_hal_subghz_idle,
.load_preset = subghz_device_cc1101_int_interconnect_load_preset,
.set_frequency = subghz_device_cc1101_int_interconnect_set_frequency,
.is_frequency_valid = furi_hal_subghz_is_frequency_valid,
.set_async_mirror_pin = furi_hal_subghz_set_async_mirror_pin,
.get_data_gpio = furi_hal_subghz_get_data_gpio,
.set_tx = furi_hal_subghz_tx,
.flush_tx = furi_hal_subghz_flush_tx,
.start_async_tx = subghz_device_cc1101_int_interconnect_start_async_tx,
.is_async_complete_tx = furi_hal_subghz_is_async_tx_complete,
.stop_async_tx = furi_hal_subghz_stop_async_tx,
.set_rx = furi_hal_subghz_rx,
.flush_rx = furi_hal_subghz_flush_rx,
.start_async_rx = subghz_device_cc1101_int_interconnect_start_async_rx,
.stop_async_rx = furi_hal_subghz_stop_async_rx,
.get_rssi = furi_hal_subghz_get_rssi,
.get_lqi = furi_hal_subghz_get_lqi,
.rx_pipe_not_empty = furi_hal_subghz_rx_pipe_not_empty,
.is_rx_data_crc_valid = furi_hal_subghz_is_rx_data_crc_valid,
.read_packet = furi_hal_subghz_read_packet,
.write_packet = furi_hal_subghz_write_packet,
};
const SubGhzDevice subghz_device_cc1101_int = {
.name = SUBGHZ_DEVICE_CC1101_INT_NAME,
.interconnect = &subghz_device_cc1101_int_interconnect,
};

8
lib/subghz/devices/cc1101_int/cc1101_int_interconnect.h Normal file
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@@ -0,0 +1,8 @@
#pragma once
#include "../types.h"
#define SUBGHZ_DEVICE_CC1101_INT_NAME "cc1101_int"
typedef struct SubGhzDeviceCC1101Int SubGhzDeviceCC1101Int;
extern const SubGhzDevice subghz_device_cc1101_int;

13
lib/subghz/devices/device_registry.h Normal file
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@@ -0,0 +1,13 @@
#pragma once
#include "registry.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const SubGhzDeviceRegistry subghz_device_registry;
#ifdef __cplusplus
}
#endif

210
lib/subghz/devices/devices.c Normal file
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@@ -0,0 +1,210 @@
#include "devices.h"
#include "registry.h"
void subghz_devices_init() {
furi_check(!subghz_device_registry_is_valid());
subghz_device_registry_init();
}
void subghz_devices_deinit(void) {
furi_check(subghz_device_registry_is_valid());
subghz_device_registry_deinit();
}
const SubGhzDevice* subghz_devices_get_by_name(const char* device_name) {
furi_check(subghz_device_registry_is_valid());
const SubGhzDevice* device = subghz_device_registry_get_by_name(device_name);
return device;
}
const char* subghz_devices_get_name(const SubGhzDevice* device) {
const char* ret = NULL;
if(device) {
ret = device->name;
}
return ret;
}
bool subghz_devices_begin(const SubGhzDevice* device) {
bool ret = false;
if(device && device->interconnect->begin) {
ret = device->interconnect->begin();
}
return ret;
}
void subghz_devices_end(const SubGhzDevice* device) {
if(device && device->interconnect->end) {
device->interconnect->end();
}
}
bool subghz_devices_is_connect(const SubGhzDevice* device) {
bool ret = false;
if(device && device->interconnect->is_connect) {
ret = device->interconnect->is_connect();
}
return ret;
}
void subghz_devices_reset(const SubGhzDevice* device) {
if(device && device->interconnect->reset) {
device->interconnect->reset();
}
}
void subghz_devices_sleep(const SubGhzDevice* device) {
if(device && device->interconnect->sleep) {
device->interconnect->sleep();
}
}
void subghz_devices_idle(const SubGhzDevice* device) {
if(device && device->interconnect->idle) {
device->interconnect->idle();
}
}
void subghz_devices_load_preset(
const SubGhzDevice* device,
FuriHalSubGhzPreset preset,
uint8_t* preset_data) {
if(device && device->interconnect->load_preset) {
device->interconnect->load_preset(preset, preset_data);
}
}
uint32_t subghz_devices_set_frequency(const SubGhzDevice* device, uint32_t frequency) {
uint32_t ret = 0;
if(device && device->interconnect->set_frequency) {
ret = device->interconnect->set_frequency(frequency);
}
return ret;
}
bool subghz_devices_is_frequency_valid(const SubGhzDevice* device, uint32_t frequency) {
bool ret = false;
if(device && device->interconnect->is_frequency_valid) {
ret = device->interconnect->is_frequency_valid(frequency);
}
return ret;
}
void subghz_devices_set_async_mirror_pin(const SubGhzDevice* device, const GpioPin* gpio) {
if(device && device->interconnect->set_async_mirror_pin) {
device->interconnect->set_async_mirror_pin(gpio);
}
}
const GpioPin* subghz_devices_get_data_gpio(const SubGhzDevice* device) {
const GpioPin* ret = NULL;
if(device && device->interconnect->get_data_gpio) {
ret = device->interconnect->get_data_gpio();
}
return ret;
}
bool subghz_devices_set_tx(const SubGhzDevice* device) {
bool ret = 0;
if(device && device->interconnect->set_tx) {
ret = device->interconnect->set_tx();
}
return ret;
}
void subghz_devices_flush_tx(const SubGhzDevice* device) {
if(device && device->interconnect->flush_tx) {
device->interconnect->flush_tx();
}
}
bool subghz_devices_start_async_tx(const SubGhzDevice* device, void* callback, void* context) {
bool ret = false;
if(device && device->interconnect->start_async_tx) {
ret = device->interconnect->start_async_tx(callback, context);
}
return ret;
}
bool subghz_devices_is_async_complete_tx(const SubGhzDevice* device) {
bool ret = false;
if(device && device->interconnect->is_async_complete_tx) {
ret = device->interconnect->is_async_complete_tx();
}
return ret;
}
void subghz_devices_stop_async_tx(const SubGhzDevice* device) {
if(device && device->interconnect->stop_async_tx) {
device->interconnect->stop_async_tx();
}
}
void subghz_devices_set_rx(const SubGhzDevice* device) {
if(device && device->interconnect->set_rx) {
device->interconnect->set_rx();
}
}
void subghz_devices_flush_rx(const SubGhzDevice* device) {
if(device && device->interconnect->flush_rx) {
device->interconnect->flush_rx();
}
}
void subghz_devices_start_async_rx(const SubGhzDevice* device, void* callback, void* context) {
if(device && device->interconnect->start_async_rx) {
device->interconnect->start_async_rx(callback, context);
}
}
void subghz_devices_stop_async_rx(const SubGhzDevice* device) {
if(device && device->interconnect->stop_async_rx) {
device->interconnect->stop_async_rx();
}
}
float subghz_devices_get_rssi(const SubGhzDevice* device) {
float ret = 0;
if(device && device->interconnect->get_rssi) {
ret = device->interconnect->get_rssi();
}
return ret;
}
uint8_t subghz_devices_get_lqi(const SubGhzDevice* device) {
uint8_t ret = 0;
if(device && device->interconnect->get_lqi) {
ret = device->interconnect->get_lqi();
}
return ret;
}
bool subghz_devices_rx_pipe_not_empty(const SubGhzDevice* device) {
bool ret = false;
if(device && device->interconnect->rx_pipe_not_empty) {
ret = device->interconnect->rx_pipe_not_empty();
}
return ret;
}
bool subghz_devices_is_rx_data_crc_valid(const SubGhzDevice* device) {
bool ret = false;
if(device && device->interconnect->is_rx_data_crc_valid) {
ret = device->interconnect->is_rx_data_crc_valid();
}
return ret;
}
void subghz_devices_read_packet(const SubGhzDevice* device, uint8_t* data, uint8_t* size) {
if(device && device->interconnect->read_packet) {
device->interconnect->read_packet(data, size);
}
}
void subghz_devices_write_packet(const SubGhzDevice* device, const uint8_t* data, uint8_t size) {
if(device && device->interconnect->write_packet) {
device->interconnect->write_packet(data, size);
}
}

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#pragma once
#include "types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct SubGhzDevice SubGhzDevice;
void subghz_devices_init();
void subghz_devices_deinit(void);
const SubGhzDevice* subghz_devices_get_by_name(const char* device_name);
const char* subghz_devices_get_name(const SubGhzDevice* device);
bool subghz_devices_begin(const SubGhzDevice* device);
void subghz_devices_end(const SubGhzDevice* device);
bool subghz_devices_is_connect(const SubGhzDevice* device);
void subghz_devices_reset(const SubGhzDevice* device);
void subghz_devices_sleep(const SubGhzDevice* device);
void subghz_devices_idle(const SubGhzDevice* device);
void subghz_devices_load_preset(
const SubGhzDevice* device,
FuriHalSubGhzPreset preset,
uint8_t* preset_data);
uint32_t subghz_devices_set_frequency(const SubGhzDevice* device, uint32_t frequency);
bool subghz_devices_is_frequency_valid(const SubGhzDevice* device, uint32_t frequency);
void subghz_devices_set_async_mirror_pin(const SubGhzDevice* device, const GpioPin* gpio);
const GpioPin* subghz_devices_get_data_gpio(const SubGhzDevice* device);
bool subghz_devices_set_tx(const SubGhzDevice* device);
void subghz_devices_flush_tx(const SubGhzDevice* device);
bool subghz_devices_start_async_tx(const SubGhzDevice* device, void* callback, void* context);
bool subghz_devices_is_async_complete_tx(const SubGhzDevice* device);
void subghz_devices_stop_async_tx(const SubGhzDevice* device);
void subghz_devices_set_rx(const SubGhzDevice* device);
void subghz_devices_flush_rx(const SubGhzDevice* device);
void subghz_devices_start_async_rx(const SubGhzDevice* device, void* callback, void* context);
void subghz_devices_stop_async_rx(const SubGhzDevice* device);
float subghz_devices_get_rssi(const SubGhzDevice* device);
uint8_t subghz_devices_get_lqi(const SubGhzDevice* device);
bool subghz_devices_rx_pipe_not_empty(const SubGhzDevice* device);
bool subghz_devices_is_rx_data_crc_valid(const SubGhzDevice* device);
void subghz_devices_read_packet(const SubGhzDevice* device, uint8_t* data, uint8_t* size);
void subghz_devices_write_packet(const SubGhzDevice* device, const uint8_t* data, uint8_t size);
#ifdef __cplusplus
}
#endif

13
lib/subghz/devices/preset.h Normal file
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#pragma once
/** Radio Presets */
typedef enum {
FuriHalSubGhzPresetIDLE, /**< default configuration */
FuriHalSubGhzPresetOok270Async, /**< OOK, bandwidth 270kHz, asynchronous */
FuriHalSubGhzPresetOok650Async, /**< OOK, bandwidth 650kHz, asynchronous */
FuriHalSubGhzPreset2FSKDev238Async, /**< FM, deviation 2.380371 kHz, asynchronous */
FuriHalSubGhzPreset2FSKDev476Async, /**< FM, deviation 47.60742 kHz, asynchronous */
FuriHalSubGhzPresetMSK99_97KbAsync, /**< MSK, deviation 47.60742 kHz, 99.97Kb/s, asynchronous */
FuriHalSubGhzPresetGFSK9_99KbAsync, /**< GFSK, deviation 19.042969 kHz, 9.996Kb/s, asynchronous */
FuriHalSubGhzPresetCustom, /**Custom Preset*/
} FuriHalSubGhzPreset;

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lib/subghz/devices/registry.c Normal file
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#include "registry.h"
#include "cc1101_int/cc1101_int_interconnect.h"
#include <flipper_application/plugins/plugin_manager.h>
#include <loader/firmware_api/firmware_api.h>
#define TAG "SubGhzDeviceRegistry"
struct SubGhzDeviceRegistry {
const SubGhzDevice** items;
size_t size;
PluginManager* manager;
};
static SubGhzDeviceRegistry* subghz_device_registry = NULL;
void subghz_device_registry_init(void) {
SubGhzDeviceRegistry* subghz_device =
(SubGhzDeviceRegistry*)malloc(sizeof(SubGhzDeviceRegistry));
subghz_device->manager = plugin_manager_alloc(
SUBGHZ_RADIO_DEVICE_PLUGIN_APP_ID,
SUBGHZ_RADIO_DEVICE_PLUGIN_API_VERSION,
firmware_api_interface);
//ToDo: fix path to plugins
if(plugin_manager_load_all(subghz_device->manager, "/any/apps_data/subghz/plugins") !=
//if(plugin_manager_load_all(subghz_device->manager, APP_DATA_PATH("plugins")) !=
PluginManagerErrorNone) {
FURI_LOG_E(TAG, "Failed to load all libs");
}
subghz_device->size = plugin_manager_get_count(subghz_device->manager) + 1;
subghz_device->items =
(const SubGhzDevice**)malloc(sizeof(SubGhzDevice*) * subghz_device->size);
subghz_device->items[0] = &subghz_device_cc1101_int;
for(uint32_t i = 1; i < subghz_device->size; i++) {
const SubGhzDevice* plugin = plugin_manager_get_ep(subghz_device->manager, i - 1);
subghz_device->items[i] = plugin;
}
FURI_LOG_I(TAG, "Loaded %zu radio device", subghz_device->size);
subghz_device_registry = subghz_device;
}
void subghz_device_registry_deinit(void) {
plugin_manager_free(subghz_device_registry->manager);
free(subghz_device_registry->items);
free(subghz_device_registry);
subghz_device_registry = NULL;
}
bool subghz_device_registry_is_valid(void) {
return subghz_device_registry != NULL;
}
const SubGhzDevice* subghz_device_registry_get_by_name(const char* name) {
furi_assert(subghz_device_registry);
if(name != NULL) {
for(size_t i = 0; i < subghz_device_registry->size; i++) {
if(strcmp(name, subghz_device_registry->items[i]->name) == 0) {
return subghz_device_registry->items[i];
}
}
}
return NULL;
}
const SubGhzDevice* subghz_device_registry_get_by_index(size_t index) {
furi_assert(subghz_device_registry);
if(index < subghz_device_registry->size) {
return subghz_device_registry->items[index];
} else {
return NULL;
}
}

40
lib/subghz/devices/registry.h Normal file
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#pragma once
#include "types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct SubGhzDevice SubGhzDevice;
void subghz_device_registry_init(void);
void subghz_device_registry_deinit(void);
bool subghz_device_registry_is_valid(void);
/**
* Registration by name SubGhzDevice.
* @param name SubGhzDevice name
* @return SubGhzDevice* pointer to a SubGhzDevice instance
*/
const SubGhzDevice* subghz_device_registry_get_by_name(const char* name);
/**
* Registration subghzdevice by index in array SubGhzDevice.
* @param index SubGhzDevice by index in array
* @return SubGhzDevice* pointer to a SubGhzDevice instance
*/
const SubGhzDevice* subghz_device_registry_get_by_index(size_t index);
/**
* Getting the number of registered subghzdevices.
* @param subghz_device SubGhzDeviceRegistry
* @return Number of subghzdevices
*/
size_t subghz_device_registry_count(void);
#ifdef __cplusplus
}
#endif

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#pragma once
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#include <furi.h>
#include <furi_hal.h>
#include "preset.h"
#include <flipper_application/flipper_application.h>
#define SUBGHZ_RADIO_DEVICE_PLUGIN_APP_ID "subghz_radio_device"
#define SUBGHZ_RADIO_DEVICE_PLUGIN_API_VERSION 1
typedef struct SubGhzDeviceRegistry SubGhzDeviceRegistry;
typedef struct SubGhzDevice SubGhzDevice;
typedef bool (*SubGhzBegin)(void);
typedef void (*SubGhzEnd)(void);
typedef bool (*SubGhzIsConnect)(void);
typedef void (*SubGhzReset)(void);
typedef void (*SubGhzSleep)(void);
typedef void (*SubGhzIdle)(void);
typedef void (*SubGhzLoadPreset)(FuriHalSubGhzPreset preset, uint8_t* preset_data);
typedef uint32_t (*SubGhzSetFrequency)(uint32_t frequency);
typedef bool (*SubGhzIsFrequencyValid)(uint32_t frequency);
typedef void (*SubGhzSetAsyncMirrorPin)(const GpioPin* gpio);
typedef const GpioPin* (*SubGhzGetDataGpio)(void);
typedef bool (*SubGhzSetTx)(void);
typedef void (*SubGhzFlushTx)(void);
typedef bool (*SubGhzStartAsyncTx)(void* callback, void* context);
typedef bool (*SubGhzIsAsyncCompleteTx)(void);
typedef void (*SubGhzStopAsyncTx)(void);
typedef void (*SubGhzSetRx)(void);
typedef void (*SubGhzFlushRx)(void);
typedef void (*SubGhzStartAsyncRx)(void* callback, void* context);
typedef void (*SubGhzStopAsyncRx)(void);
typedef float (*SubGhzGetRSSI)(void);
typedef uint8_t (*SubGhzGetLQI)(void);
typedef bool (*SubGhzRxPipeNotEmpty)(void);
typedef bool (*SubGhzRxIsDataCrcValid)(void);
typedef void (*SubGhzReadPacket)(uint8_t* data, uint8_t* size);
typedef void (*SubGhzWritePacket)(const uint8_t* data, uint8_t size);
typedef struct {
SubGhzBegin begin;
SubGhzEnd end;
SubGhzIsConnect is_connect;
SubGhzReset reset;
SubGhzSleep sleep;
SubGhzIdle idle;
SubGhzLoadPreset load_preset;
SubGhzSetFrequency set_frequency;
SubGhzIsFrequencyValid is_frequency_valid;
SubGhzSetAsyncMirrorPin set_async_mirror_pin;
SubGhzGetDataGpio get_data_gpio;
SubGhzSetTx set_tx;
SubGhzFlushTx flush_tx;
SubGhzStartAsyncTx start_async_tx;
SubGhzIsAsyncCompleteTx is_async_complete_tx;
SubGhzStopAsyncTx stop_async_tx;
SubGhzSetRx set_rx;
SubGhzFlushRx flush_rx;
SubGhzStartAsyncRx start_async_rx;
SubGhzStopAsyncRx stop_async_rx;
SubGhzGetRSSI get_rssi;
SubGhzGetLQI get_lqi;
SubGhzRxPipeNotEmpty rx_pipe_not_empty;
SubGhzRxIsDataCrcValid is_rx_data_crc_valid;
SubGhzReadPacket read_packet;
SubGhzWritePacket write_packet;
} SubGhzDeviceInterconnect;
struct SubGhzDevice {
const char* name;
const SubGhzDeviceInterconnect* interconnect;
};